UPD63 Datasheet, PDF (26/68 Pages) NEC – 4-BIT SINGLE-CHIP MICROCONTROLLER FOR INFRARED REMOTE CONTROL TRANSMISSION

µPD63, 63A, 64
6. RESET PIN
The system reset takes effect by inputting low level to the RESET pin.
While the RESET pin is at low level, the system clock oscillation circuit is stopped and the XIN and XOUT pins
are fixed to the GND.
If the RESET pin is raised from low level to high level, it executes the program from the 0 address after counting
246 to 694 of the system clock (fX).
Figure 6-1. Reset Operation by RESET Input
RESET
Wait
(246 to 694)/fX + α
0 address start
OPERATING mode or Oscillation
OPERATING
STANDBY mode
stopped HALT mode
mode
α : Oscillation growth time
The RESET pin outputs low level when the POC circuit (mask option) is in operation.
Caution When connecting a reset IC to the RESET pin, ensure that the IC is of the N-ch open drain output
type.
Table 6-1. Hardware Statuses After Reset
Hardware
PC (10 bits)
SP (1 bit)
Data
R0 = DP
memory R1-RF
Accumulator (A)
Status flag (F)
Carry flag (CY)
Timer (10 bits)
Port register P0
P1
Control register P3
P4
• RESET Input in Operation
• Resetting by Internal POC Circuit in Operation
• Resetting by Other Factors^{Note 1}
000H
0B
000H
Undefined
Undefined
0B
0B
000H
FFH
×FH^{Note 2}
03H
26H
• RESET Input During STANDBY Mode
• Resetting by the Internal POC Circuit During
STANDBY Mode
Previous status retained
Notes 1. The following resets are available.
• Reset when executing the HALT instruction (when the operand value is illegal or does not satisfy
the precondition)
• Reset when executing the RLZ instruction (when A = 0)
• Reset by stack pointer’s overflow or underflow
2. Refers to the value by the KI pin status.
In order to prevent malfunction, be sure to input a low level to more than one of pins KI0 to KI3 when
reset is released (when RESET pin changes from low level to high level, or POC is released due to
supply voltage startup).
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