UPD720133 Datasheet, PDF (23/36 Pages) NEC – MOS Integrated Circuit

µPD720133
IDEΠϯλϑΣʔεɾϒϩοΫ
PIOϞʔυ
߲ç ç ໨
ུ߸
Mode 0
Mode 1
Mode 2
Mode 3
Cycle time (min.)
t0
Address setup time (min.)
t1
16 bits DIOR/DIOW pulse width (min.)
t2
8 bits DIOR/DIOW pulse width (min.)
600
383
240
180
70
50
30
30
165
125
100
80
290
290
290
80
DIOR/DIOW recovery time (min.)
t2i
DIOW data setup time (min.)
t3
DIOW data hold time (min.)
t4
DIOR data setup time (min.)
t5
DIOR data hold time (min.)
t6
DIOR 3-state delay time (max.)
t6Z
Address hold time (min.)
t9
IORDY read data valid time (min.) ^஫
tRD
IORDY setup time (min.) ^஫
tA
IORDY pulse width (max.) ^஫
tB
IORDY inactive to Hi-Z time (max.) ^஫
tC
-
60
30
50
5
30
20
0
35
1250
5
-
45
20
35
5
30
15
0
35
1250
5
-
30
15
20
5
30
10
0
35
1250
5
70
30
10
20
5
30
10
0
35
1250
5
஫ IORDY͸Mode 0 - 2Ͱ͸ΦϓγϣϯͰ͢ɻҰํɼMode 3 - 4Ͱ͸ඞਢͱͳΓ·͢ɻ
Mode 4
120
25
70
70
25
20
10
20
5
30
10
0
35
1250
5
୯Ґ
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Multi Word DMAϞʔυ
߲ç ç ໨
Cycle time (min.)
DIOR/DIOW pulse width (min.)
DIOR data access time (max.)
DIOR data hold time (min.)
DIOR data setup time (min.)
DIOW data setup time (min.)
DIOW data hold time (min.)
DMACK data setup time (min.)
DMACK data hold time (min.)
DIOR negate pulse width (min.)
DIOW negate pulse width (min.)
DIOR-DMARQ delay time (max.)
DIOW-DMARQ delay time (max.)
DMACK 3-state delay time (max.)
CS setup time (min.)
CS hold time (min.)
ུ߸
t0
tD
tE
tF
tGr
tGw
tH
tI
tJ
tKr
tKw
tLr
tLw
tZ
tM
tN
Mode 0
480
215
150
5
100
100
20
0
20
50
215
120
40
20
50
15
Mode 1
150
80
60
5
30
30
15
0
5
50
50
40
40
25
30
10
Mode 2
120
70
50
5
20
20
10
0
5
25
25
35
35
25
25
10
୯Ґ
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
σʔλɾγʔτʢ࢑ఆʣ S17100JJ2V0DS
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