UPC1851B Datasheet, PDF (22/60 Pages) NEC – I2C BUS-COMPATIBLE US MTS PROCESSING LSI

µPC1851B
3. I²C BUS INTERFACE
The µPC1851B uses a 2-wire serial bus developed by Philips. The serial clock line (SCL) and serial data line
(SDA) employ the 2-wire configuration as shown in Figure 3-1.
The µPC1851B contains an I²C bus interface circuit, eleven (8-bit) read/write registers, and one read-only register.
Serial Clock Line (SCL)
The master CPU outputs a serial clock to achieve data synchronicity. The µPC1851B receives serial data based
on this clock. The input level is CMOS-compatible. The clock frequency is from 0 to 100 kHz.
Serial Data Line (SDA)
The master CPU outputs data synchronously with the serial clock. The µPC1851B receives this data based on
the serial clock. The input level is CMOS-compatible
Figure 3-1. Internal Equivalent Circuit of Interface Pins
SCL
SDA
RP
RP
µ PC1851B
For SCL and SDA pins, a protection diode on the VCC side is deleted not so as to pull the voltage of I²C bus line
down to 0 V while the power supply is off (VCC = 0 V).
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Data Sheet S13417EJ2V0DS00