UPD44324082 Datasheet, PDF (20/40 Pages) NEC – 36M-BIT DDRII SRAM 2-WORD BURST OPERATION

µPD44324082, 44324092, 44324182, 44324362
Read and Write Timing
NOP
READ
READ NOP
(burst of 2) (burst of 2)
NOP
WRITE WRITE READ
(burst of 2) (burst of 2) (burst of 2)
1
2
3
4
5
6
7
8
9
10
TKHKH
K
TKHKL TTKKLLKKHH
TKHK#H
TK#HKH
K#
LD#
R, W#
Address
DQ
CQ
CQ#
C
C#
TIVKH
TKHIX
TAVKH TKHAX
A0
A1
Qx2
TKHCH
TKHCH
TCHQX1
TCHQV
A2
A3
A4
TKHDX
TKHDX
TDVKH
Q01 Q02 Q11 Q12
TDVKH
D21 D22 D31 D32
TCHQX
TCHQV
TCHQZ
TCHQX
TCHCQX
TCHCQV
TCHCQX
TCHCQV
TKHKL TKLKH TKHKH TKHK#HTK#HKH
Q41 Q42
TCQHQX
TCQHQV
Remarks 1. Q01 refers to output from address A0.
Q02 refers to output from the next internal burst address following A0, etc.
2. Outputs are disabled (high impedance) 2.5 clocks after the last READ (LD# = L, R, W# = H) is input in
the sequences of [READ]-[NOP].
3. The second NOP cycle at the cycle "5" is not necessary for correct device operation;
however, at high clock frequencies it may be required to prevent bus contention.
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Data Sheet M16780EJ3V0DS