NP160N04TDG Datasheet, PDF (2/8 Pages) NEC – SWITCHING N-CHANNEL POWER MOS FET

NP160N04TDG
ELECTRICAL CHARACTERISTICS (TA = 25°C)
CHARACTERISTICS
SYMBOL
TEST CONDITIONS
Zero Gate Voltage Drain Current
IDSS
Gate Leakage Current
IGSS
Gate to Source Threshold Voltage
Forward Transfer Admittance ^Note
Drain to Source On-state Resistance ^Note
VGS(th)
| yfs |
RDS(on)1
VDS = 40 V, VGS = 0 V
VGS = ±20 V, VDS = 0 V
VDS = VGS, ID = 250 μA
VDS = 5 V, ID = 40 A
VGS = 10 V, ID = 80 A
<R> Input Capacitance
RDS(on)2
Ciss
VGS = 4.5 V, ID = 80 A
VDS = 25 V,
<R>
<R>
Output Capacitance
Reverse Transfer Capacitance
Coss
Crss
VGS = 0 V,
f = 1 MHz
Turn-on Delay Time
td(on)
VDD = 20 V, ID = 80 A,
Rise Time
tr
VGS = 10 V,
Turn-off Delay Time
td(off)
RG = 0 Ω
Fall Time
Total Gate Charge ^Note
tf
QG
VDD = 32 V,
Gate to Source Charge
QGS
VGS = 10 V,
Gate to Drain Charge
Body Diode Forward Voltage ^Note
QGD
VF(S-D)
ID = 160 A
IF = 160 A, VGS = 0 V
Reverse Recovery Time
Reverse Recovery Charge
trr
IF = 160 A, VGS = 0 V,
Qrr
di/dt = 100 A/μs
Note Pulsed test
MIN.
1.5
37
TYP. MAX.
1
±100
2.0
2.5
94
1.6
2.0
2.2
5.4
10500 15750
980 1470
630 1140
35
80
55
140
107 220
17
50
180 270
30
57
0.9
1.5
49
60
UNIT
μA
nA
V
S
mΩ
mΩ
pF
pF
pF
ns
ns
ns
ns
nC
nC
nC
V
ns
nC
TEST CIRCUIT 1 AVALANCHE CAPABILITY
TEST CIRCUIT 2 SWITCHING TIME
D.U.T.
RG = 25 Ω
L
PG.
50 Ω
VDD
VGS = 20 → 0 V
BVDSS
IAS
ID
VDD
VDS
Starting Tch
TEST CIRCUIT 3 GATE CHARGE
D.U.T.
RG
PG.
VGS
0
τ
τ = 1 μs
Duty Cycle ≤ 1%
RL
VDD
VGS
VGS
Wave Form
10%
0
VDS
90%
VDS
VDS
0
Wave Form
td(on)
VGS
90%
90%
10% 10%
tr td(off) tf
ton
toff
D.U.T.
IG = 2 mA
RL
PG.
50 Ω
VDD
2
Data Sheet D18761EJ2V0DS