UPD720114_07 Datasheet, PDF (19/32 Pages) NEC – MOS INTEGRATED CIRCUIT

Parameter
Symbol
Conditions
Full-speed Electrical Characteristics (Continued)
Consecutive frame interval jitter
tRFI
No clock adjustment
Source jitter total (including frequency
Note
tolerance) (Figure 2-13):
To next transition
tDJ1
For paired transitions
tDJ2
Source jitter for differential transition to SE0
transition (Figure 2-14)
tFDEOP
Receiver jitter (Figure 2-15):
To Next Transition
tJR1
For Paired Transitions
tJR2
Source SE0 interval of EOP (Figure 2-14)
tFEOPT
Receiver SE0 interval of EOP (Figure 2-14) tFEOPR
Width of SE0 interval during differential
tFST
transition
Hub differential data delay (Figure 2-11)
(with cable)
(without cable)
tHDD1
tHDD2
Hub differential driver jitter (including cable)
(Figure 2-11):
To next transition
tHDJ1
For paired transitions
tHDJ2
Data bit width distortion after SOP (Figure
2-11)
tFSOP
Hub EOP delay relative to tHDD (Figure 2-12) tFEOPD
Hub EOP output width skew (Figure 2-12)
tFHESK
High-speed Electrical Characteristics
Rise time (10% to 90%)
tHSR
Fall time (90% to 10%)
tHSF
Driver waveform
See Figure 2-9.
High-speed data rate
tHSDRAT
Microframe interval
tHSFRAM
Consecutive microframe interval difference tHSRFI
Data source jitter
Receiver jitter tolerance
Hub data delay (without cable)
See Figure 2-9.
See Figure 2-4.
tHSHDD
Hub data jitter
Hub delay variation range
See Figure 2-4, Figure 2-9.
tHSHDV
Note Excluding the first transition from the Idle state.
μPD720114
(2/4)
Min.
Max.
Unit
42
ns
−3.5
+3.5
ns
−4.0
+4.0
ns
−2
+5
ns
−18.5
−9
160
82
+18.5
ns
+9
ns
175
ns
ns
14
ns
70
ns
44
ns
−3
+3
ns
−1
+1
ns
−5
+5
ns
0
15
ns
−15
+15
ns
500
ps
500
ps
479.760
124.9375
480.240
125.0625
4 high-
speed
Mbps
μs
Bit
times
36 high-
speed+4 ns
Bit
times
5 high-
speed
Bit
times
Data Sheet S17462EJ4V0DS
19