UPD705100 Datasheet, PDF (19/66 Pages) NEC – V830TM 32-BIT MICROCONTROLLER

µPD705100
6. CLOCK CONTROLLER
6.1 Operation Modes
The V830 supports two clock stop functions, namely, sleep mode and stop mode. Transition from one mode to
another is made by executing special instructions HALT or STBY. The following lists the features of these modes:
Table 6-1. Operation Modes
V830 Internal state
Entry to mode
Escape from mode
Sleep mode
Internal clock stop
PLL operation continuous
Bus hold acceptable
Built-in RAM/cache data hold
HALT instruction
Maskable interrupt/NMI/reset
Stop mode
Internal clock stop
PLL operation stop
Bus hold unacceptable
Built-in RAM/cache data hold
STBY instruction
NMI/reset
6.1.1 Sleep mode
The V830 enters sleep mode upon the execution of a HALT instruction. On the other hand, escape from sleep
mode can be realized by a maskable interrupt, NMI, or reset operation.
In sleep mode, bus hold requests can be accepted. During bus hold, the status becomes high impedance and no
halt acknowledge status is output. At the end of bus hold, a halt acknowledge status is output in sync with the rising
edge of a bus clock pulse.
6.1.2 Stop mode
The V830 enters stop mode when an STBY instruction is executed. On the other hand, escape from stop mode
can be realized using an NMI or a reset operation. The power consumption in stop mode is less than that in the sleep
mode because the PLL circuit stops.
Also, no bus hold requests are accepted in the stop mode.
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