UPD75036 Datasheet, PDF (18/58 Pages) NEC – 4 BIT SINGLE-CHIP MICROCOMPUTER

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VDD
VDD
µPD75036
Fig. 5-1 Block Diagram of the Clock Generator
XT1
Subsystem
fXT
clock generator
XT2
X1
Main system fX
clock generator
X2
Clock timer
 _{• Multifunction timers}



•
•
Basic interval timer (BT)
Timer/event counter
 ^{• Serial interface}
 • Clock timer
 _{• A/D converter}



•
(successive approximation)
INT0 noise eliminator
 ^{• Clock output circuit}
1/2 to 1/4096
Frequency divider
1/2 1/16
WM.3
SCC
SCC3
SCC0
PCC
PCC0
PCC1
4
PCC2
HALT^Note
PCC3
STOP^Note
Oscillator
disable
signal
Selec-
tor
Selec-
tor
HALT F/F
S
RQ
Frequency
divider
1/4
Φ
 •CPU
 •INT0 noise




eliminator
•Clock
output
 ^circuit
PCC2, PCC3
clear signal
STOP F/F
QS
R
Wait release signal from BT
RESET signal
Standby release signal from
interrupt control circuit
Note Instruction execution
Remarks 1. fX : Main system clock frequency
2. fXT : Subsystem clock frequency
3. Φ = CPU clock
4. PCC: Processor clock control register
5. SCC: System clock control register
6. One clock cycle (tCY) of the CPU clock (Φ) is equal to one machine cycle of an instruction. See
Chapter 10 for details of tCY.
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