UPD16835A Datasheet, PDF (17/32 Pages) NEC – MONOLITHIC QUAD H BRIDGE DRIVER CIRCUIT

µPD16835A
Table 5-8. 2nd Byte Data Configuration (Standard data)
Bit
Data
D7
0 or 1
D6
0 or 1
D5
0 or 1
D4
0 or 1
D3
0 or 1
D2
0 or 1
D1
0 or 1
D0
0 or 1
Rotation direction ENABLE
Number of pulses
<3rd and 4th bytes>
The 3rd and 4th bytes select the pulse cycle of the α channel and which of the two reference voltages, created in
the initial mode, is to be used (CURRENT SETα).
The pulse cycle is specified using 15 bits : bits D0 (least significant bit) to D7 of the 3rd byte, and bits D0 to D6
(most significant bit) of the 4th byte. The pulse cycle can be set to a value in the range of 0.25 to 8191.75 µs in units
of 0.25 µs (with a 4-MHz clock).
CURRENT SETα is specified by bit D7 of the 4th byte. When this bit is “0”, reference voltage 1 (EVRα1) is
selected; when it is “1”, reference voltage 2 (EVRα2) is selected. For further information, refer to the description of the
6th byte of the initial data.
Table 5-9. 4th Byte Data Configuration (Standard data) Table 5-10. 3rd Byte Data Configuration (Standard data)
Bit
Data
D7 D6 D5 D4 D3 D2 D1 D0
0 or 1 0 or 1 0 or 1 0 or 1 0 or 1 0 or 1 0 or 1 0 or 1
D7 D6 D5 D4 D3 D2 D1 D0
0 or 1 0 or 1 0 or 1 0 or 1 0 or 1 0 or 1 0 or 1 0 or 1
CURRENT SETα Most significant
bit
Least significant bit
(Reference) 6th Byte Data Configuration for Initial Data
Bit
D7
D6
D5
D4
D3
Data
0 or 1 0 or 1 0 or 1 0 or 1 0 or 1
Remark Bits D4 to D7 : Reference voltage 2 (EVR α2)
Bits D0 to D3 : Reference voltage 1 (EVR α1)
D2
0 or 1
D1
0 or 1
D0
0 or 1
<5th byte>
The 5th byte specifies the rotation direction of the β channel, enables output of the β channel, and the number of
pulses (252 pulses MAX.) during the 1VD period (in one cycle of FF2) of the β channel.
Bit D7 is used to specify the rotation direction. The rotation is in the forward direction (CW mode) when this bit is
“0”; it is in the reverse direction (CCW mode) when the bit is “1”.
Bit D6 is used to enable the output of the β channel. The β channel goes into a high impedance state when this bit
is “0”; it is in the conduction mode when the bit is “1”.
The number of pulses is set by bits D0 to D5. It is set by six bits in terms of software. However, the actual circuit
uses an 8-bit decoder with the low-order two bits fixed to “0”. Therefore, the number of pulses that is actually
generated during start up wait time + start up drive wait (FF2) cycle is the number of pulses input x 4. The number of
pulses can be set in a range of 0 to 252 and in units of 4 pulses.
Data Sheet S15973EJ1V0DS
17