UPD23C64040JL Datasheet, PDF (13/24 Pages) NEC – 64M-BIT MASK-PROGRAMMABLE ROM 8M-WORD BY 8-BIT (BYTE MODE) / 4M-WORD BY 16-BIT (WORD MODE) PAGE ACCESS MODE

µPD23C64040JL, 23C64080JL
Read Cycle Timing Chart 2 (Page Access Mode)
Upper address^{Note 1}
A2 to A21
(Input)
A3 to A21
tACC
/CE (Input)
tCE
/OE or OE (Input)
Page address^{Note 1}
A−1^{Note 2}, A0, A1
A−1^{Note 2}, A0, A1, A2
(Input)
O0
O8
to
to
O7,
O15^Note
4
(Output)
tOE
tPAC ^{Note 5}
tPAC ^{Note 5}
tOH
tOH
High-Z
Data Out Data Out
tDF ^{Note 3}
tOH
Data Out ^High-Z
Notes 1. The address differs depending on the product as follows.
Part Number
Upper address
Page address
µPD23C64040JL
A2 to A21
A–1, A0, A1
µPD23C64080JL
A3 to A21
A–1, A0, A1, A2
2. During WORD mode, A–1 is O15.
3. tDF is the time from inactivation of Chip Enable input (/CE) or Output Enable input (/OE or OE) to
high impedance state output.
4. During BYTE mode, O8 to O14 are high impedance and O15 is A–1.
5. The definition of page access time is as follows.
[ µPD23C64040JL ]
Page access time
Upper address (A2 to A21)
inputs condition
/CE input condition
/OE or OE input condition
tPAC
Before tACC – tPAC
Before tCE – tPAC
Before stabilizing of page
address (A–1, A0, A1)
[ µPD23C64080JL ]
Page access time
tPAC
Upper address (A3 to A21)
inputs condition
Before tACC – tPAC
/CE input condition
Before tCE – tPAC
/OE or OE input condition
Before stabilizing of page
address (A–1, A0, A1, A2)
Data Sheet M16065EJ3V0DS
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