UPD16341 Datasheet, PDF (13/20 Pages) NEC – 96-BIT AC-PDP DRIVER

µ PD16341
Switching Characteristics (TA = +25 °C, VDD1 = 5.0 V, VDD2 = 110 V, VSS1 = VSS2 = 0 V, Logic CL = 15 pF,
Driver CL = 50 pF, tr = tf = 6.0 ns)
Parameter
Symbol
Conditions
MIN.
TYP.
MAX.
Unit
Propagation Delay Time
• Rise Time
• ^{Fall Time}
Maximum Clock Frequency
Input Capacitance
tPHL1
CLK ↑ → A/B
tPLH1
tPHL2
/LE ↓ → O1 to O96
tPLH2
tPHL3
/HBLK → O1 to O96
tPLH3
tPHL4
/LBLK → O1 to O96
tPLH4
tPHZ
HZ → O1 to O96
tPZH
RL = 10 kΩ
tPLZ
tPZL
tTLH
O1 to O96
tTLZ
O1 to O96
tTZH
RL = 10 kΩ
tTHL
O1 to O96
tTHZ
O1 to O96
tTZL
RL = 10 kΩ
fMAX. When data is read, duty = 50 %
40
Cascade connection :
25
Duty = 50 %
CI
34
ns
34
ns
180
ns
180
ns
165
ns
165
ns
160
ns
160
ns
300
ns
180
ns
300
ns
180
ns
360
ns
3
µs
360
ns
450
ns
3
µs
450
ns
MHz
MHz
15
pF
Timing Requirement (TA = –40 to +85 °C, VDD1 = 4.5 to 5.5 V, VSS1 = VSS2 = 0 V, tr = tf = 6.0 ns)
Parameter
Symbol
Conditions
MIN.
TYP.
MAX.
Unit
Clock Pulse Width
PWCLK(H)
12
ns
PWCLK(L)
Latch Enable Pulse Width
PW/LE
12
ns
• Blank Pulse Width
PW/BLK /HBLK, /LBLK
600
ns
HZ Pulse Width
PWHZ RL = 10 kΩ
3.3
µs
/CLR Pulse Width
PW/CLR
12
ns
Data Setup Time
tSETUP
4
ns
Data Hold Time
tHOLD
6
ns
Latch Enable Time
t/LE1
12
ns
t/LE2
12
ns
/CLR Timing
t/CLR
6
ns
Data Sheet S14076EJ2V0DS00
13