UPD61051 Datasheet, PDF (10/106 Pages) NEC – MOS INTEGRATED CIRCUIT MPEG2 AUDIO/VIDEO ENCODER

µPD61051, 61052
1.4 Audio Input/output Interface
After hardware reset, it becomes input. OALRCK, OABCK and OABD connect with 3.3 V VDD through the 10 kΩ
pull up resistance. Firmware controls input/output of those pins.
Name
OALRCK
OABCK
OABD
AMCLK
IO
Pin
Number
IO 4
IO 5
IO 6
I2
Left/Right clock
Bit clock
Bit data
Audio clock
Function
Active
Polarity
↑
↑
1.5 Stream Input Interface
Stream input corresponds to MPEG TS/PS stream. When slave mode (MPEG2-TS input with using valid signal),
data input is possible to select 8 bits parallel data or serial data mode. When serial data mode, data input to IS0.
Active polarity of ISREQ is selected by the port setup register.
Active polarity of ISCLK/ISSTB, ISSYNC ISERR and ISVLD are selected by firmware. These are unsettled after
the turning on.
Name
ISREQ
ISCLK/ISSTB
ISCLK/ISSTB
ISSYNC
ISVLD
IS1/ISERR
IS1/ISERR
IS7 to IS2, IS0
IO
Pin
Number
Function
O 55
Stream data request
Only parallel interface, this pin is active.
After reset, default is active low.
I 53
Stream data strobe
After reset, default is ISCLK.
I 53
Stream data clock
After reset, default is active high edge.
I 52
Stream data synchronization
After reset, default is active high.
I 54
Stream data valid
After reset, default is active low.
I 43
Stream error
After reset, default is active high.
I 43
Stream data input
I 51,49, 47 Stream data input
to 44, 42
Active
Polarity
Remark In this table, means of reset are hardware reset by the RESET pin and ALL RESET of the reset register.
10
Data Sheet S15082EJ4V0DS