UPG153TB_01 Datasheet, PDF (1/4 Pages) NEC – L, S Band SPDT GaAs MMIC Switch

PRELIMINARY DATA SHEET
UPG153TB
L, S Band SPDT GaAs MMIC Switch _UPG155TB
FEATURES
• LOW INSERTION LOSS:
LINS = 0.5 dB TYP (UPG153TB), 0.6 dB TYP (UPG155TB)
at VCONT = +3.0 V/0 V, f = 1 GHz
• HIGH LINEARITY SWITCHING:
Pin (0.1 dB) = +29.0 dBm TYP (UPG153TB)
Pin (0.1 dB) = +30.5 dBm TYP (UPG155TB)
at VCONT = +3.0 V/0 V, f = 2 GHz
• SMALL 6 PIN MINI-MOLD PACKAGE:
Size: 2.0 x 1.25 x 0.9 mm
DESCRIPTION
The UPG153TB and UPG155TB are L-band SPDT (Single
Pole Double Throw) GaAs FET switches for digital cellular or
cordless telephone application. The devices can operate from
100 MHz to 2.5 GHz with low insertion loss. These devices are
housed in an original 6 pin super mini-mold package similar to
SOT363.
NEC's stringent quality assurance and test procedures assure
the highest reliability and performance.
APPLICATION
• L, S-BAND DIGITAL CELLULAR OR CORDLESS
TELEPHONE
• PCS, WLAN AND WLL APPLICATIONS
ELECTRICAL CHARACTERISTICS
(Unless otherwise specified, TA = 25°C, VCONT1 = 3 V, VCONT2 = 0 V or VCONT1 = 0 V, VCONT2 = 3 V; off chip DC blocking capacitor value, 51 pF)
PART NUMBER
PACKAGE OUTLINE
SYMBOLS
PARAMETERS AND CONDITIONS
LINS
ISOL
RLIN
RLOUT
PIN(0.1 dB)
PIN(1 dB)
tsw
ICONT
Insertion Loss at f = 0.1 to 1 GHz
f = 2 GHz
f = 2.5 GHz
Isolation at f = 0.1 to 2 GHz
f = 2.5 GHz
f = 1 GHz
Input Return Loss at f = 0.1 to 2 GHz
Input Return Loss at f = 0.1 to 2 GHz
Input Power at 0.1 dB Compression Point, f = 2 GHz
Input Power at 1 dB Compression Point, f = 2 GHz
Switching Speed
Control Current at VCONT = 3 V/0 V, no RF signal
UNITS
dB
dB
dB
dB
dB
dB
dB
dB
dBm
dBm
ns
µA
UPG153TB
S06
MIN
TYP
MAX
0.5
0.65
0.7
0.9
0.9
10
13
10
15
18.5
11
15
11
15
29
31
33
30
20
50
UPG155TB
S06
MIN
TYP
MAX
0.6
0.8
0.75
1.0
0.9
13
16
10
18
21.5
11
15
11
15
30.5
32
34
30
20
50
Note:
1. It is necessary to use DC blocking capacitors for the RF input and RF output. The value of DC blocking capacitors should be chosen to
accommodate the frequency of operation. The range of recommended DC blocking capacitor value is less than 100 pF.
2. The distance between IC's GND pin and ground pattern of substrate should be as short as possible to avoid parasitics.
California Eastern Laboratories