UPD705101 Datasheet, PDF (1/72 Pages) NEC – 32-BIT MICROPROCESSOR

DATA SHEET
MOS INTEGRATED CIRCUIT
µPD705101
V831^TM
32-BIT MICROPROCESSOR
DESCRIPTION
The µPD70501 (V831) is a 32-bit RISC microprocessor for embedded control applications, with a high-performance
32-bit V830^TM processor core and many peripheral functions such as a DRAM/ROM controller, 4-channel DMA
controller, real-time pulse unit, serial interface, and interrupt controller.
In addition to high interrupt response speed and optimized pipeline structure, the V831 offers sum-of-products
operation instructions, concatenated shift instructions, and high-speed branch instructions to realize multimedia
functions, and therefore, can provide high performance in multimedia systems such as internet/intra-net systems, car
navigation systems, high-performance televisions, and color FAXes.
Detailed explanations of the functions, etc. are given in the following user’s manuals. Be sure to read the
manuals before designing your systems.
V831 User’s Manual -Handware
: U12273E
V830 Family^TM User’s Manual -Architecture : U12496E
FEATURES
• CPU function
• V830-compatible instructions
• Instruction cache
: 4 KB
• Instruction RAM
: 4 KB
• Data cache
: 4 KB
• Data RAM
: 4 KB
• Minimum number of instruction
execution cycles
: 1 cycle
• Number of general purpose
registers
: 32 bits × 32
• Memory space and I/O space
: 4 GB each
• Interrupt/exception function
• Non-maskable : External input : 1
• Maskable : External input : 8 (of which 4 are
multiplexed with internal sources)
Internal source: 11 types
• Bus control function
• Wait control function
• Memory access control function
• DMA controller : 4 channel
• Serial interface function
• Asynchronous serial interface (UART): 1 channel
• Clocked serial interface (CSI)
: 1 channel
• Dedicated baud rate generator (BRG) : 1 channel
• Timer/counter function
• 16-bit timer/event counter : 1 channel
• 16-bit interval timer
: 1 channel
• Port function
: 3 I/O ports
• Clock generation function : PLL clock synthesizer
• Standby function
: HALT and STOP modes
• Debug function
• Debug-dedicated synchronous serial
interface
: 1 channel
• Trace-dedicated interface
: 1 channel
The information in this document is subject to change without notice.
Document No. U12979EJ1V0DS00 (1st edition)
Date Published January 1998 N
Printed in Japan
©
1998