UPD4701A Datasheet, PDF (1/16 Pages) NEC – MOS INTEGRATED CIRCUIT

DATA SHEET
MOS INTEGRATED CIRCUIT
µPD4701A
INCREMENTAL ENCODER COUNTER
DESCRIPTION
The µPD4701A is a counter for an X, Y 2-axis incremental encoder. When a two-phase encoder signal is input
for the X and Y axes, direction discrimination and computation is performed, and count data is output in 8-bit parallel
form. In addition, a 3-contact-point input buffer is incorporated, which is useful for applications which use a pointing
device such as a mouse or track-ball. The CPU checks the switch input flag or count flag and reads the 12-bit count
data in two operations, one for the lower byte and one for the upper byte. The key input flag is output together with
the count data in the upper byte.
FEATURES
• X, Y 2-axis incremental encoder counter
• Counter input (Schmitt-triggered input)
X axis:
Y axis:
XA,
YA,
XB
YB
2-phase
2-phase
signal
signal

4-multiplication
count
method
used
• Counters: 12-bit binary up/down counters (2 sets, X & Y)
Reset value: 000H
• Count data output: 8-bit parallel latch output × 2 (including key input flag)
• On-chip 3-contact-point key input buffer circuit
• CMOS
• Single +5 V power supply
PIN CONFIGURATION (Top View)
PIN NAMES
XA, YA : A-phase inputs
XB, YB : B-phase inputs
RIGHT _
LEFT _ Key inputs
MIDDLE 
XA
1
XB
2
RESET X
3
YA
4
24
VDD
23
D7
22
D6
21
D5
CS
X/Y
U/L
D0 to 7
CF
SF
: Chip Select
: X/Y Counter Select
: Upper/Lower Byte Select
: Data outputs
: Count flag
: Count flag
RESET
RESET
X
Y

Counter
reset inputs
YB
5
RESET Y
6
RIGHT
7
LEFT
8
MIDDLE
9
SF
10
20
D4
19
D3
18
D2
17
D1
16
D0
15
CS
CF
11
14
X/Y
VSS
12
13
U/L
Document No. IC-3303 (1st edition)
(O. D. No. IC-6947A)
Date Published March 1997 P
Printed in Japan
©
1993