UPD4564323 Datasheet, PDF (1/84 Pages) NEC – 64M-bit Synchronous DRAM 4-bank, LVTTL

DATA SHEET
MOS INTEGRATED CIRCUIT
µPD4564323 for Rev. E
64M-bit Synchronous DRAM
4-bank, LVTTL
Description
The µPD4564323 is a high-speed 67,108,864-bit synchronous dynamic random-access memory, organized as
524,288 words × 32 bits × 4 banks.
The synchronous DRAMs achieved high-speed data transfer using the pipeline architecture.
All inputs and outputs are synchronized with the positive edge of the clock.
The synchronous DRAMs are compatible with Low Voltage TTL (LVTTL).
These products are packaged in 86-pin TSOP (II).
Features
• Fully Synchronous Dynamic RAM, with all signals referenced to a positive clock edge
• Pulsed interface
• Possible to assert random column address in every cycle
• Quad internal banks controlled by BA0 and BA1 (Bank Select)
• ×32 organization
• Byte control by DQM0, DQM1, DQM2 and DQM3
• Programmable Wrap sequence (Sequential / Interleave)
• Programmable burst length (1, 2, 4, 8 and full page)
• Programmable /CAS latency (2 and 3)
• Automatic precharge and controlled precharge
• CBR (Auto) refresh and self refresh
• Single 3.3 V ± 0.3 V power supply
• LVTTL compatible inputs and outputs
• 4,096 refresh cycles / 64 ms
• Burst termination by Burst stop command and Precharge command
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all devices/types available in every country. Please check with local NEC representative for
availability and additional information.
Document No. M14376EJ2V0DS00 (2nd edition)
The mark • shows major revised points.
Date Published December 1999 NS CP (K)
Printed in Japan
©
1999