UPD42S18165L Datasheet, PDF (1/48 Pages) NEC – 3.3 V OPERATION 16 M-BIT DYNAMIC RAM 1 M-WORD BY 16-BIT, EDO, BYTE READ/WRITE MODE

DATA SHEET
MOS INTEGRATED CIRCUIT
µPD42S18165L, 4218165L
3.3 V OPERATION 16 M-BIT DYNAMIC RAM
1 M-WORD BY 16-BIT, EDO, BYTE READ/WRITE MODE
Description
The µPD42S18165L, 4218165L are 1,048,576 words by 16 bits CMOS dynamic RAMs with optional EDO.
EDO is a kind of the page mode and is useful for the read operation.
Besides, the µPD42S18165L can execute CAS before RAS self refresh.
The µPD42S18165L, 4218165L are packaged in 50-pin plastic TSOP (II) and 42-pin plastic SOJ.
Features
• EDO (Hyper page mode)
• 1,048,576 words by 16 bits organization
• Single +3.3 V ±0.3 V power supply
• Fast access and cycle time
Part number
Power consumption
Active (MAX.)
µPD42S18165L-A50, 4218165L-A50
612 mW
µPD42S18165L-A60, 4218165L-A60
540 mW
µPD42S18165L-A70, 4218165L-A70
504 mW
Access time
(MAX.)
50 ns
60 ns
70 ns
R/W cycle time
(MIN.)
84 ns
104 ns
124 ns
EDO (Hyper page mode)
cycle time (MIN.)
20 ns
25 ns
30 ns
• The µPD42S18165L can execute CAS before RAS self refresh
Part number
µPD42S18165L
µPD4218165L
Refresh cycle
Refresh
1,024 cycles/128 ms
1,024 cycles/16 ms
CAS before RAS self refresh,
CAS before RAS refresh,
RAS only refresh, Hidden refresh
CAS before RAS refresh,
RAS only refresh,
Hidden refresh
Power consumption at standby
(MAX.)
0.54 mW
(CMOS level input)
1.8 mW
(CMOS level input)
The information in this document is subject to change without notice.
Document No. M10562EJ8V0DS00 (8th edition)
The mark shows major revised points.
Date Published January 1997 N
Printed in Japan
©
1995