UPD30550 Datasheet, PDF (1/27 Pages) NEC – VR5500™ 64-/32-BIT MICROPROCESSOR

PRELIMINA^DDR^AAY^TT^AAPR^SSO^HHD^EEU^EE^TCTT INFORMATION
MOS INTEGRATED CIRCUIT
µPD30550
VR5500^TM
64-/32-BIT MICROPROCESSOR
DESCRIPTION
The µPD30550 (VR5500) is a member of the VR Series^TM of RISC (Reduced Instruction Set Computer)
microprocessors. It is a high-performance 64-/32-bit microprocessor that employs the RISC architecture developed by
MIPS^TM.
The VR5500 allows selection of a 64-bit or 32-bit bus width for the system interface, and can operate using
protocols compatible with the VR5000 Series^TM and VR5432^TM.
Detailed function descriptions are provided in the • VR5500 User’s Manual (U16044E)
user’s manual. Be sure to read the manual before designing.
FEATURES
• MIPS 64-bit RISC architecture
• High-speed operation processing
• Two-way superscaler super pipeline
• 300 MHz product: 603 MIPS
400 MHz product: 804 MIPS
• High-speed translation lookaside buffer (TLB)
(48 entries)
• Address space
• Physical: 36 bits (64-bit bus selected)
32 bits (32-bit bus selected)
• Virtual: 40 bits (in 64-bit mode)
31 bits (in 32-bit mode)
• On-chip floating-point unit (FPU)
• Supports sum-of-products instructions
• On-chip primary cache memory
(instruction/data: 32 KB each)
• 2-way set associative
• Supports line lock feature
• 64-/32-bit address/data multiplexed bus
• Bus width selectable during reset
• Bus protocol compatibility with existing products
retained
• Maximum operating frequency
• 300 MHz product: Internal 300 MHz, external 133
MHz
400 MHz product: Internal 400 MHz, external 133
MHz
• External/internal multiplication factor selectable from
×2 to ×5.5 by increments of .5
• Conforms to MIPS I, II, III, IV and MIPS64 instruction
sets. Instruction set extensions supported include
product-sum operation instruction, rotate instruction,
register scan instruction, and instruction for low power
mode.
• Hardware debug functions supported are N-Wire and
JTAG.
• Supply voltage
Core block:
1.5 V ±5% (300 MHz product)
1.6 to 1.7 V (400 MHz product)
I/O block:
3.3 V ±5%, 2.5 V ±5%
The information contained in this document is being issued in advance of the production cycle for the
device. The parameters for the device may change before final production or NEC Corporation, at its own
discretion, may withdraw the device prior to its production.
Not all devices/types available in every country. Please check with local NEC representative for
availability and additional information.
©
Document No. U15700EJ1V0DS01 (2nd edition)
Date Published September 2002 N CP(K)
Printed in USA
2002
2001