UPD29F064115-X Datasheet, PDF (1/32 Pages) NEC – 64M-BIT CMOS LOW-VOLTAGE DUAL OPERATION FLASH MEMORY 4M-WORD BY 16-BIT (WORD MODE) PAGE MODE

DATA SHEET
MOS INTEGRATED CIRCUIT
µPD29F064115-X
64M-BIT CMOS LOW-VOLTAGE DUAL OPERATION FLASH MEMORY
4M-WORD BY 16-BIT (WORD MODE)
PAGE MODE
Description
The µPD29F064115-X is a flash memory organized of 67,108,864 bits and 142 sectors. Sectors of this memory can
be erased at a low voltage (1.65 to 1.95 V, 1.8 to 2.1 V ) supplied from a power source, or the contents of the entire
chip can be erased. Memory organization is 4,194,304 words × 16 bits, so that the memory can be programmed in
word units. µPD29F064115-X can be read high speed with page mode.
The µPD29F064115-X can be read while its contents are being erased or programmed. The memory cell is divided
into four banks. While sectors in any bank are being erased or programmed, data can be read from the other three
banks thanks to the simultaneous execution architecture. The banks are 8M bits, 24M bits, 24M bits and 8M bits.
Input /output voltage is supplied to 2.7 to 3.3 V.
Because the µPD29F064115-X enables the boot sector to be erased, it is ideal for storing a boot program. In
addition, program code that controls the flash memory can be also stored, and the program code can be programmed
or erased without the need to load it into RAM. 16 small sectors for storing parameters are provided, each of which
can be erased in 4K words units.
Once a program or erase command sequence has been executed, an automatic program or automatic erase
function internally executes program or erase and verification automatically. The programming time is about 0.5
seconds per sector. The erase time is less than 1 second per sector.
Because the µPD29F064115-X can be electrically erased or programmed by writing an instruction, data can be
reprogrammed on-board after the flash memory has been installed in a system, making it suitable for a wide range of
applications.
This flash memory is packed in 48-pin PLASTIC TSOP (I), 63-pin TAPE FBGA and 85-pin TAPE FBGA.
Features
• Four bank organization enabling simultaneous execution of program / erase and read
• High-speed read with page mode
• Bank organization : 4 banks (8M bits + 24M bits + 24M bits + 8M bits)
• Memory organization : 4,194,304 words × 16 bits
• Sector organization : 142 sectors (4K words × 16 sectors, 32K words × 126 sectors)
The boot sector is located at the highest address (sector) and the lowest address (sector)
• 3-state output
• Automatic program
• Program suspend / resume
• Unlock bypass program
• Automatic erase
• Chip erase
• Sector erase (sectors can be combined freely)
• Erase suspend / resume
• Program / Erase completion detection
• Detection through data polling and toggle bits
• Detection through RY (/BY) pin
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all devices/types available in every country. Please check with local NEC representative for
availability and additional information.
Document No. M16062EJ2V0DS00 (2nd edition)
Date Published September 2002 NS CP (K)
Printed in Japan
The mark # shows major revised points.
©
2002