UPD178076 Datasheet, PDF (1/72 Pages) NEC – 8-BIT SINGLE-CHIP MICROCONTROLLER

DATA SHEET
MOS INTEGRATED CIRCUIT
µPD178076,178078,178096,178098
8-BIT SINGLE-CHIP MICROCONTROLLER
DESCRIPTION
The µPD178076, 178078, 178096, and 178098 are 8-bit single-chip CMOS microcontrollers containing hardware
for digital tuning systems.
These microcontrollers employ a 78K/0 series architecture CPU and allow easy access to internal memories at
high speed and easy control of peripheral hardware units. The high-speed 78K/0 series instructions are ideal for
system control.
As peripheral hardware, a prescaler, PLL frequency synthesizer, and frequency counter for digital tuning systems
are provided, as well as many I/O ports, timers, A/D converter, serial interface, and a power-ON clear circuit. In
addition, the µPD178076 and 178078 have an asynchronous serial interface (UART) mode, and the µPD178096 and
178098 have an IEBus^TM controller.
Moreover, a flash memory model, the µPD178F098, that operates in the same supply voltage range as the mask
ROM models, and various development tools are also under development.
For the detailed functional description, refer to the following User’s Manuals:
µPD178078, 178098 Subseries User’s Manual : U12790E
78K/0 Series User’s Manual - Instruction : U12326E
FEATURES
• ^{High-capacity ROM and RAM}
Part Number
Item Program Memory (ROM)
Data Memory
Internal high-speed RAM Internal buffer RAM Internal extension RAM
µPD178076, 178096
48K bytes
µPD178078, 178098
60K bytes
• Instruction cycle:
0.32 µs (with crystal resonator of fX = 6.3 MHz)
• Many internal hardware units
General-purpose I/O ports, A/D converter, serial
interface (UART mode: µPD178076 and 178078
only), IEBus controller (µPD178096 and 178098
only), timers, frequency counter, power-ON clear
circuit
1024 bytes
32 bytes
1024 bytes
2048 bytes
• Hardware for PLL frequency synthesizer
dual modulus prescaler, programmable divider,
phase comparator, charge pump
• Vectored interrupt sources
• µPD178076, 178078: 22
• µPD178096, 178098: 21
• Supply voltage
:VDD = 4.5 to 5.5 V (during PLL and CPU
operations)
:VDD = 3.5 to 5.5 V (during CPU operation)
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all devices/types available in every country. Please check with local NEC representative for availability
and additional information.
Document No. U12885EJ3V0DS00
The mark shows major revised points.
Date Published June 2000 N CP(K)
Printed in Japan
©
1997, 2000