UPD178004 Datasheet, PDF (1/56 Pages) NEC – 8-BIT SINGLE-CHIP MICROCONTROLLER

DATA SHEET
MOS INTEGRATED CIRCUIT
µ PD178004, 178006, 178016, 178018
8-BIT SINGLE-CHIP MICROCONTROLLER
The µPD178004, 178006, 178016 and 178018 are 8-bit single-chip CMOS microcontrollers that incorporate
hardware for digital tuning systems.
The CPU uses the 78K/0 architecture and high-speed access to internal memory and control of peripheral
hardware are easy to implement. Also, the instructions used are the high-speed 78K/0 instructions, suitable for
system control.
The rich assortment of peripheral hardware includes an input/output port, 8-bit timer, A/D converter, serial
interface, power-ON clear circuits, as well as a pre-scaler for digital tuning, a PLL frequency synthesizer and a
frequency counter.
The µPD178P018, one-time PROM or EPROM versions which can be operated in the same supply voltage
range as for the mask ROM versions, and various development tools, are also available.
For more information on functions, refer to the following User’s Manuals. Be sure to read them when
designing.
µPD178018 Subseries User’s Manual: U11410E
78K/0 Series User’s Manual Instruction: IEU-1372
FEATURES
• Internal high-capacity ROM and RAM
Items
Product Name
µPD178004
µPD178006
µPD178016
µPD178018
Program Memory
ROM
Internal High-Speed RAM
32 Kbytes
1024 bytes
48 Kbytes
60 Kbytes
Data Memory
Buffer RAM
32 bytes
Internal Expanded RAM
Not provided
2048 bytes
• Instruction Cycle: 0.44 µs (4.5-MHz crystal oscillator used)
• Large array of on-chip peripheral hardware
General-purpose input/output port, A/D converter, serial interface, timer, frequency counter, power-ON clear
circuits.
• On-chip hardware for a PLL frequency synthesizer.
Dual modulus pre-scaler, programmable divider, phase comparator, charge pump.
• Vector Interrupts: 17
• Supply Voltage: VDD = 4.5 to 5.5 V (during PLL operation)
VDD = 3.5 to 5.5 V (during CPU operation, when the system clock is fX/2 or lower)
VDD = 4.5 to 5.5 V (during CPU operation, when the system clock is fX)
The information in this document is subject to change without notice.
Document No. U11800EJ2V1DS00 (2nd Edition)
Date Published March 1997 N
Printed in Japan
* ^{The mark shows major revised points.}
©
1997