UPC8158K_01 Datasheet, PDF (1/5 Pages) NEC – AGC/UP-CONVERTER WITH IQ MODULATOR

AGC/UP-CONVERTER _UPC8158K
WITH IQ MODULATOR
FEATURES
• SUPPLY VOLTAGE:
VCC = 2.7 to 4.0 V, ICC = 28 mA @ VCC = 3.0 V
• BUILT-IN LPF:
Suppresses spurious multipled by TX local (LO1)
• AGC AMPLIFIER INSTALLED IN LOCAL PORT OF
UPCONVERTER:
GCR = 35 dB MIN. @ fout = 1.5 GHz
• EXCELLENT PERFORMANCE:
Padj = -65dBc TYP. @ ∆f = ±50 KHz, EVM = 1.2 %rms TYP.
• EXTERNAL IF FILTER:
Can be applied between modulator output and
up converter input terminal
APLICATIONS
• Digital cellular phones
(PDC800M, PDC1.5G,TDMA1900 and so on)
• Wireless Communiaction Systems
(MMDS, Broadband wireless access)
INTERNAL BLOCK DIAGRAM
22 21 20 19 18 17 16 15
AGCcont
Up-Mix
23
14
24
13
AGC
Reg
25
12
LPF
26
Reg
11
27
10
28 I/Q-Mix
9
Phase
Shifter
1 2 3 45 6 7 8
DESCRIPTION
The UPC8158K is a silicon microwave monolithic integrated
circuit designed as a quadrature modulator for digital mobile
communication systems. This MMIC consist of a 0.8 GHz to
1.5 GHz up-converter and 100 MHz to 300 MHz quadrature
modulator which are equipped with AGC and power save
functions. This configuration suits IF modulation systems and
is packaged in a 28-pin QFN suitable for high density
mounting. The chip is manufactured using NEC's 20 GHz fT
silicon bipolar process NESAT^TM III to realize low power
consumption. Consequently the UPC8158K can contribute to
make RF blocks smaller size, higher performance and lower
power consumption.
ELECTRICAL CHARACTERISTICS (TA = 25°C, VCC1 = VCC2 = VCC3 = 3.0 V, VPS/VAGC = 2.5 V)
SYMBOLS
ICC (TOTAL)
ICC(PS) TOTAL
PRFout1
PRFout2
LOL
ImR
IM3(I/Q)
GCR
EVM
Padj
Pout(8fLO1)
TPS(Rise)
TPS(Fall)
ZI/Q
II/Q
ZLO1
PART NUMBER
PACKAGE OUTLINE
PARAMETERS AND CONDITIONS
UP-CONVERTER + QUADRATURE MODULATOR TOTAL
Total Circuit Current, No input signal
Total Circuit Current at Power Save Mode, VPS ≤ 0.5 V(low), No input signal
Total Output Power 1, VAGC = 2.5 V
Total Output Power 2, VAGC = 1.0 V
LO Carrier Leak, fLOL = fLO1 + fLO2
Image Rejection (Side Band Leak)
I/Q 3rd Order Distortion
AGC Gain Control Range, VAGC = 2 V →1 V
Error Vector Magnitude, MOD Pattern PN9
Adjacent Channel Interference, ∆f = ±50KHz, MOD Pattern: PN9
Spurious Suppression, fLO1 × 8, fLO1 × 8 (image)^Note
Power Save Rise Time, VPS(Low) → VPS(High)
Power Save Fall Time, VPS(High) → VPS(Low)
I/Q Input Impedance, Between pin I/Ib, Q/Qb
I/Q Input Bias Current, Between pin I/Ib, Q/Qb
LO1 Input VSWR, fLO1 = 100 M to 300 MHz
UNITS
mA
µA
dBm
dBm
dBc
dBc
dBc
dB
%rms
dBc
dBc
µs
µs
kΩ
µA
-
UPC8158K
MIN
TYP
MAX
23.7
-15
-56.5
35
80
28
0.3
-11.5
-52
-40
-40
-50
40
1.2
-65
-70
2
2
200
5
1.5 :1
37.6
10
-8
-46.5
-30
-30
-30
3.0
-60
-65
5
5
13
Note:
1. Without external LC between Fil1 and Fil2 pin on this frequency conditions. Spectrum analyzer conditions: VBW = 300 Hz, RBW = 300 Hz.
California Eastern Laboratories