UPC4094 Datasheet, PDF (1/12 Pages) NEC – J-FET INPUT LOW-OFFSET DUAL OPERATIONAL AMPLIFIER

DATA SHEET
BIPOLAR ANALOG INTEGRATED CIRCUIT
µPC4094
J-FET INPUT LOW-OFFSET DUAL OPERATIONAL AMPLIFIER
Dual operational amplifier µPC4094 is a high-speed version of the µPC4092. NEC's unique high-speed PNP
transistor (fT = 300 MHz) in the output stage realizes a high slew rate of 25 V/µs under voltage-follower conditions
without an oscillation problem. Zener-zap resistor trimming in the input stage produces excellent offset voltage and
temperature drift characteristics.
With AC performance characteristics that are two times better than conventional bi-FET operation amplifiers, the
µPC4094 is ideal for fast integrators, active filters, and other high-speed circuit applications.
FEATURES
• Stable operation with 220 pF capacitive load
• Low input offset voltage and offset voltage
±3 mV (MAX.)
±7 µV/°C (TYP.) temperature drift
• Very low input bias and offset currents
• Low noise : en = 19 nV/ √Hz (TYP.)
• Output short circuit protection
• High input impedance ... J-FET Input Stage
• Internal frequency compensation
• High slew rate: 25 V/µs (TYP.)
ORDERING INFORMATION
Part Number
µPC4094C
µPC4094G2
Package
8-pin plastic DIP (300 mil)
8-pin plastic SOP (225 mil)
EQUIVALENT CIRCUIT (1/2 Circuit)
V⁺
Q9
Q6
II
Q1
Q2
OUT
Q7
IN
C1
D1
Q10
 HIGH SPEED
 _PNP

Q5
Q3
Q4
Q8
TRIMMED
V^−
PIN CONFIGURATION
(Top View)
µ PC4094C, 4094G2
OUT1 1
1
−+
II1 2
IN1 3
8 V⁺
7 OUT2
2
+−
6 II2
V^− 4
5 IN2
The information in this document is subject to change without notice.
Document No. G13907EJ1V0DS00 (1st edition)
Date Published December 1998 N CP(K)
Printed in Japan
©
1998