UPC4093 Datasheet, PDF (1/12 Pages) NEC – J-FET INPUT LOW-OFFSET OPERATIONAL AMPLIFIER

DATA SHEET
BIPOLAR ANALOG INTEGRATED CIRCUIT
µPC4093
J-FET INPUT LOW-OFFSET OPERATIONAL AMPLIFIER
The µPC4093 operational amplifier is a high-speed version of the µPC4091. NEC's unique high-speed PNP
transistor (fT = 300 MHz) in the output stage realizes a high slew rate of 25 V/µs under voltage-follower conditions
without an oscillation problem. Zener-zap resistor trimming in the input stage produces excellent offset voltage and
temperature drift characteristics.
With AC performance characteristics that are two times better than conventional bi-FET operation amplifiers, the
µPC4093 is ideal for fast integrators, active filters, and other high-speed circuit applications.
FEATURES
• Stable operation with 220 pF capacitive load
• Low input offset voltage and offset voltage null
capability
±2.5 mV (MAX.)
±7 µV/°C (TYP.) temperature drift
• Very low input bias and offset currents
• Low noise : en = 19 nV/ √Hz (TYP.)
• Output short circuit protection
• High input impedance ... J-FET Input Stage
• Internal frequency compensation
• High slew rate: 25 V/µs (TYP.)
ORDERING INFORMATION
Part Number
µPC4093C
µPC4093G2
EQUIVALENT CIRCUIT
(2)
II
Q1
Q2
IN
(3)
Q5
Q3
Q4
(1)
(5)
OFFSET
NULL
TRIMMED
OFFSET
NULL
Package
8-pin plastic DIP (300 mil)
8-pin plastic SOP (225 mil)
Q6
Q7
C1
D1
V⁺
(7)
Q9
OUT
(6)
Q10
HIGH SPEED
PNP
Q8
(4)
V^–
PIN CONFIGURATION
(Top View)
µPC4093C, 4093G2
OFFSET
NULL
1
8 NC
II 2
7 V⁺
IN 3
−+
6 OUT
V^− 4
OFFSET
5 _NULL
Remark NC : No Connection
The information in this document is subject to change without notice.
Document No. G13906EJ1V0DS00 (1st edition)
Date Published December 1998 N CP(K)
Printed in Japan
©
1998