UPC4092 Datasheet, PDF (1/12 Pages) NEC – J-FET INPUT LOW-OFFSET DUAL OPERATIONAL AMPLIFIER

DATA SHEET
BIPOLAR ANALOG INTEGRATED CIRCUIT
µPC4092
J-FET INPUT LOW-OFFSET DUAL OPERATIONAL AMPLIFIER
The µPC4092 dual operational amplifier offers high input impedance, low offset voltage, high slew rate, and stable
AC operating characteristics. NEC's unique high-speed PNP transistor (fT = 300 MHz) in the output stage solves the
oscillation problem of current sinking with a large capacitive load. Zener-zap resistor trimming in the input stage
produces excellent offset voltage and temperature drift characteristics.
FEATURES
• Stable operation with 10000 pF capacitive load
• Low input offset voltage
±3 mV (MAX.)
±7 µV/°C (TYP.) temperature drift
• Very low input bias and offset currents
ORDERING INFORMATION
• Low noise : en = 19 nV/ √Hz (TYP.)
• Output short circuit protection
• High input impedance ... J-FET Input Stage
• Internal frequency compensation
• High slew rate: 15 V/µs (TYP.)
Part Number
µPC4092C
µPC4092G2
Package
8-pin plastic DIP (300 mil)
8-pin plastic SOP (225 mil)
EQUIVALENT CIRCUIT (1/2 Circuit)
V⁺
Q9
Q6
II
Q1
Q2
OUT
Q7
IN
C1
D1
Q10
 HIGH SPEED 
 _PNP

Q5
Q3
Q4
Q8
PIN CONFIGURATION
(Top View)
µ PC4092C, 4092G2
OUT1 1
1
−+
II1 2
IN1 3
8 V⁺
7 OUT2
2
+−
6 II2
V^− 4
5 IN2
TRIMMED
V^−
The information in this document is subject to change without notice.
Document No. G13905EJ1V0DS00 (1st edition)
Date Published December 1998 N CP(K)
Printed in Japan
©
1998