UPC4091 Datasheet, PDF (1/12 Pages) NEC – J-FET INPUT LOW-OFFSET OPERATIONAL AMPLIFIER

DATA SHEET
BIPOLAR ANALOG INTEGRATED CIRCUIT
µPC4091
J-FET INPUT LOW-OFFSET OPERATIONAL AMPLIFIER
The µPC4091 operational amplifier offers high input impedance, low offset voltage, high slew rate, and stable AC
operating characteristics. NEC's unique high-speed PNP transistor (fT = 300 MHz) in the output stage solves the
oscillation problem of current sinking with a large capacitive load. Zener-zap resistor trimming in the input stage
produces excellent offset voltage and temperature drift characteristics.
FEATURES
• Stable operation with 10000 pF capacitive load
• Low input offset voltage and offset voltage null
capability
±2.5 mV (MAX.)
±7 µV/°C (TYP.) temperature drift
• Very low input bias and offset currents
• Low noise : en = 19 nV/ √Hz (TYP.)
• Output short circuit protection
• High input impedance ... J-FET Input Stage
• Internal frequency compensation
• High slew rate: 15 V/µs (TYP.)
ORDERING INFORMATION
Part Number
µPC4091C
µPC4091G2
EQUIVALENT CIRCUIT
(2)
II
Q1
Q2
IN
(3)
Q5
Q3
Q4
(1)
(5)
OFFSET
NULL
TRIMMED
OFFSET
NULL
Package
8-pin plastic DIP (300 mil)
8-pin plastic SOP (225 mil)
Q6
Q7
C1
D1
V⁺
(7)
Q9
OUT
(6)
Q10
HIGH SPEED
PNP
Q8
(4)
V^–
PIN CONFIGURATION
(Top View)
µPC4091C, 4091G2
OFFSET
NULL
1
8 NC
II 2
7 V⁺
IN 3
–+
6 OUT
V^– 4
OFFSET
5 _NULL
Remark NC : No Connection
The information in this document is subject to change without notice.
Document No. G13904EJ1V0DS00 (1st edition)
Date Published November 1998 N CP(K)
Printed in Japan
©
1998