NE32500 Datasheet, PDF (1/8 Pages) NEC – C to Ka BAND SUPER LOW NOISE AMPLIFIER N-CHANNEL HJ-FET CHIP

DATA SHEET
HETERO JUNCTION FIELD EFFECT TRANSISTOR
NE32500, NE27200
C to Ka BAND SUPER LOW NOISE AMPLIFIER
N-CHANNEL HJ-FET CHIP
DESCRIPTION
NE32500 and NE27200 are Hetero Junction FET chip that utilizes the hetero junction between Si-doped AlGaAs
and undoped InGaAs to create high mobility electrons. Its excellent low noise and high associated gain make it suitable
for commercial systems, industrial and space applications.
FEATURES
• Super Low Noise Figure & High Associated Gain
NF = 0.45 dB TYP., Ga = 12.5 dB TYP. at f = 12 GHz
• Gate Length : Lg = 0.2 µm
• Gate Width : Wg = 200 µm
ORDERING INFORMATION
PART NUMBER
NE32500
NE27200
QUALITY GRADE
Standard (Grade D)
Special, specific (Grade C and B)
ABSOLUTE MAXIMUM RATINGS (TA = 25 ˚C)
Drain to Source Voltage
VDS
4.0
V
Gate to Source Voltage
VGS
–3.0
V
Drain Current
ID
IDSS
mA
Total Power Dissipation
Ptot*
200
mW
Channel Temperature
Tch
175
°C
Storage Temperature
Tstg
–65 to +175
°C
* Chip mounted on a Alumina heatsink (size: 3 × 3 × 0.6^t)
ELECTRICAL CHARACTERISTICS (TA = 25 ˚C)
PARAMETER
SYMBOL
Gate to Source Leak Current
IGSO
Saturated Drain Current
IDSS
Gate to Source Cutoff Voltage VGS(off)
Transconductance
gm
Thermal Resistance
Rth*
Noise Figure
NF
Associated Gain
Ga
MIN.
–
20
–0.2
45
–
–
11.0
TYP.
0.5
60
–0.7
60
–
0.45
12.5
MAX.
10
90
–2.0
–
260
0.55
–
UNIT
µA
mA
V
mS
˚C/W
dB
dB
TEST CONDITIONS
VGS = –3 V
VDS = 2 V, VGS = 0 V
VDS = 2 V, ID = 100 µA
VDS = 2 V, ID = 10 mA
channel to case
VDS = 2 V, ID = 10 mA, f = 12 GHz
RF performance is determined by packaging and testing 10 chips per wafer.
Wafer rejection criteria for standard devices is 2 rejects per 10 samples.
Document No. P11512EJ2V0DS00 (2nd edition)
Date Published January 1997 N
Printed in Japan
©
1996