MC-4516DA726 Datasheet, PDF (1/16 Pages) NEC – 16 M-WORD BY 72-BIT SYNCHRONOUS DYNAMIC RAM MODULE REGISTERED TYPE

DATA SHEET
MOS INTEGRATED CIRCUIT
MC-4516DA726
16 M-WORD BY 72-BIT SYNCHRONOUS DYNAMIC RAM MODULE
REGISTERED TYPE
Description
The MC-4516DA726 is a 16,777,216 words by 72 bits synchronous dynamic RAM module on which 9 pieces of
128M SDRAM: µPD45128841 are assembled.
These modules provide high density and large quantities of memory in a small space without utilizing the surface-
mounting technology on the printed circuit board.
Decoupling capacitors are mounted on power supply line for noise reduction.
Features
• 16,777,216 words by 72 bits organization (ECC type)
• Clock frequency and access time from CLK
Part number
/CAS latency
Clock frequency
(MAX.)
MC-4516DA726EFC-A80
CL = 3
125 MHz
CL = 2
100 MHz
MC-4516DA726EFC-A10
CL = 3
100 MHz
5 MC-4516DA726PFC-A80
CL = 2
CL = 3
77 MHz
125 MHz
CL = 2
100 MHz
5 ^{MC-4516DA726PFC-A10}
CL = 3
CL = 2
100 MHz
77 MHz
Access time from CLK
Module type
(MAX.)
6 ns
PC100 Registered DIMM
6 ns
Rev. 1.2 Compliant
6 ns
7 ns
6 ns
6 ns
6 ns
7 ns
• Fully Synchronous Dynamic RAM, with all signals referenced • All DQs have 10 Ω ±10 % of series resistor
to a positive clock edge
• Single 3.3 V ± 0.3 V power supply
• Pulsed interface
• LVTTL compatible
• Possible to assert random column address in every cycle • 4,096 refresh cycles / 64 ms
• Quad internal banks controlled by BA0 and BA1 (Bank Select) • Burst termination by Burst Stop command and
• Programmable burst-length (1, 2, 4, 8 and Full Page)
Precharge command
• Programmable wrap sequence (Sequential / Interleave)
• 168-pin dual in-line memory module
• Programmable /CAS latency (2, 3)
(Pin pitch = 1.27 mm)
• Automatic precharge and controlled precharge
• Registered type
• CBR (Auto) refresh and self refresh
• Serial PD
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all devices/types available in every country. Please check with local NEC representative for
availability and additional information.
Document No. M13203EJ7V0DS00 (7th edition)
The mark 5 shows major revised points.
©
Date Published February 2000 NS CP(K)
Printed in Japan
1998