AN1L3M Datasheet, PDF (1/4 Pages) NEC – on-chip resistor PNP silicon epitaxial transistor

DATA SHEET
COMPOUND TRANSISTOR
AN1L3M
on-chip resistor PNP silicon epitaxial transistor
For mid-speed switching
FEATURES
• On-chip bias resistor
(R1 = 4.7 kΩ, R2 = 4.7 kΩ)
• Complementary transistor with AA1L3M
ABSOLUTE MAXIMUM RATINGS (Ta = 25°C)
Parameter
Symbol
Ratings
Unit
Collector to base voltage
VCBO
−60
V
Collector to emitter voltage
VCEO
−50
V
Emitter to base voltage
VEBO
−10
V
Collector current (DC)
IC(DC)
−100
mA
Collector current (Pulse)
IC(pulse) *
−200
mA
Total power dissipation
PT
250
mW
Junction temperature
Tj
150
°C
Storage temperature
Tstg
−55 to +150
°C
* PW ≤ 10 ms, duty cycle ≤ 50 %
PACKAGE DRAWING (UNIT: mm)
ELECTRICAL CHARACTERISTICS (Ta = 25°C)
Parameter
Symbol
Collector cutoff current
ICBO
DC current gain
hFE1 **
DC current gain
hFE2 **
Collector saturation voltage VCE(sat) **
Low level input voltage
VIL **
High level input voltage
VIH **
Input resistance
R1
Resistance ratio
R1/R2
Turn-on time
ton
Storage time
tstg
Turn-off time
toff
** PW ≤ 350 µs, duty cycle ≤ 2 %
Conditions
VCB = −50 V, IE = 0
VCE = −5.0 V, IC = −5.0 mA
VCE = −5.0 V, IC = −50 mA
IC = −5.0 mA, IB = −0.25 mA
VCE = −5.0 V, IC = −100 µA
VCE = −0.2 V, IC = −5.0 mA
VCC = −5 V, RL = 1 kΩ
VI = −5 V, PW = 2 µs
duty cycle≤2 %
MIN.
TYP.
MAX.
Unit
100
nA
20
40
80
−
70
110
−
−0.02
−0.3
V
−1.1
−0.8
V
−3.0
−1.5
V
3.29
4.7
6.11
kΩ
0.9
1.0
1.1
−
0.5
µs
3.0
µs
5.0
µs
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all devices/types available in every country. Please check with local NEC representative for
availability and additional information.
Document No. D16168EJ1V0DS00 (1st edition)
Date Published April 2002 N CP(K)
©
Printed in Japan
21090928