AA1L3N Datasheet, PDF (1/4 Pages) NEC – On-chip resistor NPN silicon epitaxial transistor For mid-speed switching

DATA SHEET
COMPOUND TRANSISTOR
AA1L3N
on-chip resistor NPN silicon epitaxial transistor
For mid-speed switching
FEATURES
• On-chip bias resistor
(R1 = 4.7 kΩ, R2 = 10 kΩ)
• Complementary transistor with AN1L3N
PACKAGE DRAWING (UNIT: mm)
ABSOLUTE MAXIMUM RATINGS (Ta = 25°C)
Parameter
Symbol
Ratings
Unit
Collector to base voltage
VCBO
60
V
Collector to emitter voltage
VCEO
50
V
Emitter to base voltage
VEBO
5
V
Collector current (DC)
IC(DC)
100
mA
Collector current (Pulse)
IC(pulse) *
200
mA
Total power dissipation
PT
250
mW
Junction temperature
Tj
150
°C
Storage temperature
Tstg
−55 to +150
°C
* PW ≤ 10 ms, duty cycle ≤ 50 %
ELECTRICAL CHARACTERISTICS (Ta = 25°C)
Parameter
Symbol
Conditions
Collector cutoff current
ICBO
VCB = 50 V, IE = 0
DC current gain
hFE1 ** VCE = 5.0 V, IC = 5.0 mA
DC current gain
hFE2 ** VCE = 5.0 V, IC = 50 mA
Collector saturation voltage
Low level input voltage
VCE(sat) ** IC = 5.0 mA, IB = 0.25 mA
VIL ** VCE = 5.0 V, IC = 100 µA
High level input voltage
VIH ** VCE = 0.2 V, IC = 5.0 mA
Input resistance
R1
E-to-B resistance
R2
Turn-on time
Storage time
Turn-off time
ton
VCC = 5 V, RL = 1 kΩ
tstg
VI = 5 V, PW = 2 µs
toff
duty cycle≤2 %
** Pulse test PW ≤ 350 µs, duty cycle ≤ 2 %
MIN.
TYP.
MAX.
Unit
100
nA
35
60
100
−
80
230
−
0.05
0.2
V
0.9
0.6
V
3.0
1.5
V
3.29
4.7
6.11
kΩ
7
10
13
kΩ
0.2
µs
5.0
µs
6.0
µs
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all devices/types available in every country. Please check with local NEC representative for
availability and additional information.
Document No. D16163EJ1V0DS00 (1st edition)
Date Published April 2002 N CP(K)
©
Printed in Japan
21090928