2SC5432 Datasheet, PDF (1/8 Pages) NEC – NPN EPITAXIAL SILICON TRANSISTOR FOR HIGH-FREQUENCY LOW-NOISE AMPLIFICATION

PRELIMINARY DATA SHEET
SILICON TRANSISTOR
2SC5432
NPN EPITAXIAL SILICON TRANSISTOR
FOR HIGH-FREQUENCY LOW-NOISE AMPLIFICATION
FEATURE
• Ultra super mini-mold thin flat package
(1.4 mm × 0.8 mm × 0.59 mm: TYP.)
• Contains same chip as 2SC5006
ABSOLUTE MAXIMUM RATINGS (TA = 25 °C)
PARAMETER
Collector to Base Voltage
Collector to Emitter Voltage
Emitter to Base Voltage
Collector Current
Total Power Dissipation
Junction Temperature
Storage Temperature
SYMBOL
VCBO
VCEO
VEBO
IC
PT
Tj
Tstg
RATING
20
12
3
100
125
150
–65 to +150
ELECTRICAL CHARACTERISTICS (TA = 25 °C)
PACKAGE DIMENSIONS (in mm)
1.4 ± 0.05
0.8 ± 0.1
UNIT
V
V
V
mA
mW
°C
°C
2
3
1
PIN CONNECTIONS
1: Emitter
2: Base
3: Collector
PARAMETER
Collector Cut-off Current
Emitter Cut-off Current
DC Current Gain
Gain Bandwidth Product
Reverse Transfer Capacitance
Insertion Power Gain
Noise Figure
SYMBOL
ICBO
IEBO
hFE
fT
Cre
|S21e|²
NF
TEST CONDITIONS
VCB = 10 V, IE = 0
VEB = 1 V, IC = 0
VCE = 3 V, IC = 7 mA^{Note 1}
VCE = 3 V, IC = 7 mA, f = 1 GHz
VCB = 3 V, IE = 0, f = 1 MHz^{Note 2}
VCE = 3 V, IC = 7 mA, f = 1 GHz
VCE = 3 V, IC = 7 mA, f = 1 GHz
MIN.
80
3.0
7.0
TYP.
4.5
0.7
10.0
1.4
MAX.
1000
1000
145
1.5
2.5
UNIT
nA
nA
GHz
pF
dB
dB
Notes 1. Pulse measurement PW ≤ 350 µs, duty cycle ≤ 2 %
2. Collector to base capacitance measured by capacitance meter (automatic balance bridge method) when
emitter pin is connected to the guard pin.
Because this product uses high-frequency process, avoid excessive input of static electricity, etc.
The information in this document is subject to change without notice.
Document No. P13076EJ1V0DS00 (1st edition)
Date Published February 1998 N CP(K)
Printed in Japan
©
1998