ADS62P45_08 Datasheet, PDF (18/70 Pages) Texas Instruments – DUAL CHANNEL, 14-BITS, 125/105/80/65 MSPS ADC WITH DDR LVDS/CMOS OUTPUTS

ADS62P45, ADS62P44
ADS62P43, ADS62P42
SLAS561A – JULY 2007 – REVISED FEBRUARY 2008
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A7–A0
(hex)
14
D2-D0
000
001
010
011
100
101
110
111
D3
0
1
D4
0
1
D5
0
1
D7
0
1
Table 11.
D7
D6
D5
D4
D3
D2 D1 D0
<OVRD>
Over-ride bit
0
<OUTPUT
INTERFACE>
LVDS or CMOS
interface
<COARSE GAIN>
3.5 dB gain
<REF>
Internal / External
reference
<POWER DOWN
MODES>
<POWER DOWN MODES>
Normal operation
Channel A output buffer disabled
Channel B output buffer disabled
Channel A and B output buffers disabled
Global power down
Channel A standby
Channel B standby
Multiplexed mode, MUX – (only with CMOS interface)
Channel A and B data is multiplexed and output on DA10 to DA0 pins.
<REF> Reference mode
Internal reference enabled
External reference enabled
<COARSE GAIN> Coarse gain control
0 dB coarse gain
3.5 dB coarse gain
<OUTPUT INTERFACE> Output interface selection
Parallel CMOS data outputs
DDR LVDS data outputs
<OVRD> Over-ride bit – the LVDS/CMOS selection, power down and MUX modes can also be controlled using parallel pins.
By setting <OVRD> = 1, register bits LVDS <CMOS> and <POWER DOWN MODES> will over-ride the settings of the parallel
pins.
Disable over-ride
Enable over-ride
A7–A0
(hex)
16
D2–D0
000
001
010
011
100
101
110
111
D3
0
1
D4
0
1
Table 12.
D7 D6
D5
D4
D3
D2 D1
D0
0
0
0
DATA FORMAT>
2s complement or straight binary
Bit / Byte wise (LVDS only)
<TEST PATTERNS>
<TEST PATTERNS> Test Patterns to verify capture
Normal ADC operation
Outputs all zeros
Outputs all ones
Outputs toggle pattern
Outputs digital ramp
Outputs custom pattern
Unused
Unused
Bit-wise/Byte-wise selection (DDR LVDS mode ONLY)
Bit wise – Odd bits (D1, D3, D5, D7, D9) on CLKOUT rising edge and Even bits (D0, D2, D4, D6, D8, D10) on CLKOUT
falling edge
Byte wise – Lower 7 bits (D0-D6) at CLKOUT rising edge and Upper 4 bits (D7-D10) at CLKOUT falling edge
<DATA FORMAT> Data format selection
2s complement
Straight binary
18
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