MU9C8358 Datasheet, PDF (19/32 Pages) MUSIC Semiconductors – Quad 10/100Mb Ethernet Filter Interface

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The Port Target registers (A through D) allow the
operating conditions of each port to be set. Bits 3-0 are
reserved and should be set to 0H. Bits 5-4 determine what
action is taken after the DA is extracted from a frame that
was received on the appropriate MII port. Bits 7-6
determine what action is taken after the SA is extracted
from a frame that was received on the appropriate MII
port.
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