MU9C8148 Datasheet, PDF (19/24 Pages) MUSIC Semiconductors – SRT Interface

MU9C8148
No. Symbol
52 tDSHBEH
53 tDSHRDH
54 tDSHRDZ
55 tSHRDZ
56 tDVRDL
57 tDSHDZ
Motorola Mode Timing (con't)
Parameter
Min
/UDS or /LDS HIGH to /HBEN HIGH Delay
tCLCL + 3
/UDS or /LDS HIGH to /HBRDY HIGH Delay Time
3
/UDS or /LDS HIGH to /HBRDY Hi-Z Delay Time
tCLCL + 3
/CS HIGH to /HBRDY Hi-Z Delay Time
tCLCL + 3
Data Output Valid to /HBRDY LOW Setup Time
2
/UDS or /LDS HIGH to Data Output Hi-Z Delay
tCLCL + 3
Max
2 • tCLCL + 20
tCLCL + 20
2 • tCLCL + 20
tCLCL + 20
2 • tCLCL + 20
Units Notes
ns
ns
ns
ns
ns
ns
LANCAM Interface Switching Characteristics
No. Symbol Parameter
Min
Typ.
Max Units Notes
58 tELEH /E LOW Period
4 • tCLCL
ns
59 tEHEL /E HIGH Period
R • tCLCL
ns
7
60 tCDVEL Control/Data Setup Time to /E LOW
1
ns
61 tELCDX Control/Data Hold Time from /E LOW
120
ns
62 tDVEH Data Setup Time to /E HIGH
tCLCL
ns
63 tEHDX Data Hold Time to /E HIGH
0
ns
Notes
1. If there are routines running due to network activity, access to the device is arbitrated and these times will be
extended by an integer number of RXC cycles, the duration of which will be indicated by /INT going LOW.
2. For non-arbitrated accesses, tWLRDL is 3 RXC cycles for Register writes and for the first write to the
Instruction Buffer, 6 RXC cycles for the second write to the Instruction Buffer or the FIFO, and 9 RXC cyles
for LANCAM writes.
3. For non-arbitrated accesses, tRLRDL is 3 RXC cycles for Register reads, 6 RXC cycles for Instruction Buffer
and FIFO reads, and 9 RXC cycles for LANCAM reads.
4. For non-arbitrated accesses, “R” is 1 for Write cycles and 2 for Read cycles.
5. For non-arbitrated accesses, tDSLRDL is 3 RXC cycles for Register and Instruction Buffer writes, 9 RXC
cycles for LANCAM writes, 3 RXC cycles for Register reads, 6 RXC cycles for Instruction Buffer reads, and 9
RXC cycles for CAM reads.
6. Although the host interface is asynchronous, RXC is used internally to control operations. Therefore, for
modeling purposes, /WS, /RS, /UDS and /LDS can be assumed to have a 10ns setup time with respect to the
rising edge of RXC and /INT, /HBRDY and /FULL can be assumed to assert within 20ns of the rising edge of
RXC. XMATCH and XFAIL assert four RXC cycles after the /MI input is valid.
7. For a data move from DQ15-DQ0 to address, R is 3. For a data move from address to DQ15-DQ0, R is 4.
For a LANCAM register write then read, R is 8. For a LANCAM register write then write, or read then read, R
is 9. For a LANCAM register access read then write, R is 10.
TIMING DIAGRAMS
RXC
/RQ (SLAVE)
/RQI (SLAVE)
1
1
2
3
MU9C8148 ARBITRATION TIMING
19
Rev. 5.5 Draft web