MU9C2481L Datasheet, PDF (15/20 Pages) MUSIC Semiconductors – LANCAM® 1ST Family

LANCAM 1^ST Family
INSTRUCTION SET SUMMARY Continued
CYCLE Command Write
LENGTH
CYCLE TYPE
Command Read
Data Write
Data Read
Short
MOV reg, reg
TCO reg (except CT)
TCO CT (non-reset, HMA invalid)
SPS, SPD, SFR
SBR, RSC, NOP
Comparand register
(not last segment)
Mask register
(not last segment)
Medium
MOV reg, mem
TCO CT (reset)
VBC (NFA invalid)
SFT
Status register or
16-bit register
Memory array
(NFA invalid)
Comparand register
Mask register
Long
MOV mem, reg
TCO CT (non-reset, HMA valid)
CMP
VBC (NFA valid)
Memory array
(NFA valid)
Comparand register
(last segment)
Mask register
(last segment)
Memory array
Note: The specific timing requirements for Short, Medium, and Long cycles are given in the Switching Characteristics
Section under the tELEH parameter. For two cycle Command Writes (TCO reg or any instruction with “aaaH” as
the source or destination), the first cycle is short, and the second cycle will be the length given.
Table 6: Instruction Cycle Lengths
15 14
RST
R
E
S
E
T
=
0
13 12 11 10
Reserved
Must be set
=000000
9 87 6
5
43
21
0
CAM/RAM Part. Comp. Mask AR Inc/Dec Reserved
64 CAM/0 RAM = 000
48 CAM/16 RAM = 001
32 CAM/32 RAM = 010
16 CAM/48 RAM = 011
48 RAM/16 CAM = 100
32 RAM/32 CAM = 101
16 RAM/48 CAM = 110
No Change = 111
None = 00
MR1 = 01
MR2 = 10
No Change
= 11
Increment
= 00
Decrement
= 01
Disable
= 10
No Change
= 11
Must be set
=00
Note: D15 reads back as 0.
Table 7: Control Register Bit Assignments
15
Rev. 1a