MU9C8338A Datasheet, PDF (14/32 Pages) MUSIC Semiconductors – 10/ 100Mb Ethernet Filter Interface

MU9C8338A 10/100Mb Ethernet Filter Interface
Software Model
System Time Stamp Current Register
The System Time Stamp Current register (STCURR)
stores the current time stamp value. It is a read-only
register, but it may be incremented by writing an arbitrary
value to the SDO_INCTS register.
Table 11: STCURR: System Time Stamp Current
Register Mapping
Name
Current Time Stamp Initial Value=00H
Location
bits [7:0]
System Maximum SA/DA Cycles Register
This register establishes the number of clock cycles that
DA and SA operations will take. This is based on the
speed of the attached LANCAM components.
Table 12 shows a CAM_SPD setting for a 120 ns speed
grade LANCAM component. 120 ns LANCAMs are no
longer available and it is recommended that when using a
90 ns LANCAM, set the register to 27H. This setting
accommodates most applications and has the added
benefit of using the least amount of power.
Table 12: SMXSADACYC: System Maximum
SA/DA Cycles Register Mapping
Name
CAM_SPD
Bits Description
5:0 27H = 120 ns (90 ns)
25H = 90 ns
20H = 70 ns
others = RESERVED
System Status Word Registers
The Status Word registers store the 32-bit LANCAM
status register value after the LANCAM entry read routine
is performed. SCSWA stores the lower 16 bits of the status
register and SCSWB stores the upper 16 bits.
Table 13: SCSW: System Status Word Register
Mapping
Register
SCSWA [15:0]
SCSWB [15:0]
LANCAM Status Register Bits
15:0
31:16
System SA Op-Code Registers
The SA Op-Code registers store the LANCAM Op-Code
values required when the MU9C8338A performs the
automatic SA search routine. SSAU stores the code
required to update an SA and SSAL stores the code
required to learn an SA. These registers have the default
values required to perform the routines described in
Built-in Routines.
Table 14: System Op-Code Register Mapping
Register
SSAU
SSAL
Bits
Default Op-Code
15:0
0368H, MOV_HM CR, MR1
15:0
0334H, MOV_NF CR, V
System LANCAM Control Register
The System LANCAM Control register enables the host
CPU to initialize and configure the LANCAMs. During
normal system operation bit 4 should be set to zero to
disable the LANCAM control bits. When the host CPU
wishes to write to the LANCAM (at initialization) bit 4 is
set to one while setting bits 3–0 to the values required for a
LANCAM data or command cycle. The data or command
to be transferred to the LANCAM should be loaded into
the SCDW0 register prior to the cycle being initiated.
Each LANCAM cycle is a four step process and is
described as follows:
1. Load SCDW0 with 16-bit data or command.
2. Load SLCCS with cycle value to take /E HIGH.
3. Load SLCCS with cycle value to take /E LOW.
4. Load SLCCS with cycle value to take /E HIGH. For
example a TCO CT command cycle would be
SCDW0= 0200H, SLCCS = 19H, 11H, 19H.
Table 15: SLCSS: System LANCAM Control
Signal Register Mapping
Name
Bits Description
/EC
0 Enable Chain
/CM
1 Command Mode
/W
2 READ/WRITE
/E
3 Enable
ENABLE 4 0 => (Normal Operation) Disable Bits [3:0]
1 => Processor Port CAM access
System Command Registers
The System Command registers allow the CPU to execute
transactions applied to a LANCAM array. There are seven
command registers and they have the prefix SDO. Each
register is used to initiate a built-in routine that allows
general LANCAM housekeeping tasks to be performed.
The housekeeping sequence is initiated by writing any
arbitrary value to the appropriate register. Descriptions of
the routines performed when SDO_ADD, SDO_DELETE,
SDO_READ, and SDO_SETADD are accessed as shown
in Built-in Routines. SDO_INCTS, SDO_INCPR, and
SDO_INCTSPR control the time stamp counters.
SDO_INCPR and SDO_INCTSPR also cause the purge
routine described in Built-in Routines to be initiated. The
MU9C8338A may hold PROC_RDY inactive, if it is
processing any high-priority DA and SA searches. The
registers and their address values can be found in Table 3.
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Rev. 0a