OP4004B Datasheet, PDF (5/7 Pages) RF Monolithics, Inc – 625.00 MHz Optical Timing Clock

The following table provides R1 and R2 values for six high-speed logic families commonly used in optical data communications systems. Note that the
OP4004B can be used with logic families that run from a negative power supply voltage by simply using a negative V_LOAD voltage.
Load Type
10k 3.3 V PECL
100k 3.3 V PECL
10k 5 V PECL
100k 5 V PECL
10k -5 V NECL
100k -5 V NECL
V_DC
1.95
1.88
3.65
3.58
-1.30
-1.42
R1
R2
120
91
120
91
180
68
180
68
240
62
240
62
V_LOAD
3.3 V
3.3 V
5.0 V
5.0 V
-5.0 V
-5.0 V
OP4004B Enable/Disable
Pin 3 on the OP4004B is the enable/disable control pin for the clock outputs. When Pin 3 is grounded, full output power is available from the clock. When
Pin 3 is pulled to Vcc, the power on the clock outputs is decreased at least 25 dB.
PLL for Generating a High Stability 625 MHz Clock
External
Reference
Internal
Reference
(holdover)
Phase
Detector
Loop Filter
Tune
÷N
+Vcc
Q
Q
OP4004B
Example OP4004B Phase-Locked Loop Application
One of the most important applications for the OP4004B is in a PLL circuit used to generate a very high quality 625.00 MHz clock. The PLL combines the
long-term stability of a precision external or internal 19.53125 MHz reference clock with the very low jitter and phase noise of the OP4004B. A block diagram
of the PLL is shown in Figure 6. A sample of the OP4004B output is divided by 32 and is compared to a 19.53125 MHz reference clock in the phase detector.
The loop filter at the output of the phase detector is set to a very low bandwidth (less than 50 Hz typical). This imparts the long-term stability of the precision
19.53125 MHz reference to the OP4004B without degrading the OP4004B's low jitter and phase noise.
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OP4004B - 3/27/08