DR8100 Datasheet, PDF (5/7 Pages) Murata Manufacturing Co., Ltd. – 916.50 MHz Transceiver Module

Theory of Operation
The DR8100 evaluation module is centered around the TR8100
Spread Spectrum ASH Transceiver. The DR8100 may operate in
backward compatible 2G mode, or in the enhanced 3G mode.
Since 3G mode requires the use of a serial I/O port to configure
internal registers, the module includes an on-board Silicon Labs
C8051F330 microcontroller to control access to the serial port.
When 2G mode is enabled the microcontroller serves no function.
When 3G mode is enabled the microcontroller constantly scans
pins 8-15 for a change of logic state. When a state change is
detected on one or more of these pins, the microcontroller
automatically updates the internal configuration registers via the
serial port of the TR8100. The microcontroller assumes full control
of the CFG pin, CFGCLK pin, and CFGDAT pin in 3G mode to
continuously update the internal registers.
The DR8100 module is designed to demonstrate the performance
of the TR8100 Spread Spectrum ASH Transceiver at 4.8kbps,
although other data rates are possible with changes in on-board
component values. See pin descriptions and refer to the TR8100
datasheet.
The DR8100 module may be mounted on a prototype assembly
using standard 0.1” spacing, 10-pin headers spaced 0.9” apart.
2G Mode Operation
The DR8100 may operate in 2G mode. See pin 15 description and
Power-up Mode Select (J2) section for mode select details. In 2G
mode, the CFGCLK pin (18) and CFGDAT pin (17) operate as
CTRL0 and CTRL1, respectively, just as for second-generation
devices. The CFGCLK and CFGDAT pins are a high impedance
input allowing external control for 2G configuration. The logic
levels on CFGCLK (CTRL0) and CFGDAT (CTRL1) control the
default 2G operation as shown below:
CFGCLK (CNTRL0)
0
1
0
1
CFGDAT (CNTRL1)
0
0
1
1
MODE
SLEEP
TX OOK
TX ASK
RX
J5 Header
Current Consumption Monitor (J5)
The current consumption of the TR8100 device may be monitored
by removing J5 and connecting an ammeter across the terminals.
When J5 is removed it isolates the TR8100 from VCC powering the
on-board processor to give a true reading of the current
consumption of only the TR8100 without the additional current
usage of the processor. J5 must be installed to power the TR8100
if not using the header for current measurement.
Power-up Mode Select (J2)
J2 is used to select the operating mode of the TR8100 device only
at power-up. The state of J2 when VCC is applied will determine
whether the board operates in 2G mode or 3G mode. Pin 2 (center
pin) of J2 is connected to Pin 19 (CFG) of the TR8100 device and
is grounded for 2G mode and functions as the chip select line for
the serial interface in 3G mode. Installing the jumper will either
connect the CFG pin of the TR8100 to GND or directly to the
processor for control in 3G mode. See the table below for power-
up jumper settings.
Setting
J2(1-2)
J2(2-3)
Power-up Mode
2G
3G
Pin 19
Connected to GND
Connected to Processor
After power-up if 3G mode is selected, pin 15 (3G Sel) must be
pulled ‘High’ to initiate the processor to operate in 3G mode.
Failure to pull pin 15 ‘High’ after power-up will cause the processor
to remain inactive.
J4
J2 Header
Programming Header (J4)
The programming header allows for custom firmware development
for the Silicon Labs C8051F330 if desired. Contact RFM for more
information about custom firmware development.
www.RFM.com E-mail: [e-mail]
©2008 by RF Monolithics, Inc.
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DR8100 - 4/8/08