DR8001 Datasheet, PDF (5/8 Pages) Murata Manufacturing Co., Ltd. – 868.35 MHz Transceiver Module

868.35 MHz
Transceiver Module
Theory of Operation
The DR8001 evaluation module is centered around the TR8001 ASH Transceiver. The DR8001 may operate in backward
compatible 2G mode, or in the enhanced 3G mode. Since 3G mode requires the use of a serial I/O port to configure internal
registers, the module includes an on-board Silicon Labs C8051F330 microcontroller to control access to the serial port. When
2G mode is enabled the microcontroller serves no function. When 3G mode is enabled the microcontroller constantly scans
pins 8-15 for a change of logic state. When a state change is detected on one or more of these pins, the microcontroller
automatically updates the internal configuration registers via the serial port of the TR8001. The microcontroller assumes full
control of the CFG pin, CFGCLK pin, and CFGDAT pin in 3G mode to continuously update the internal registers.
The DR8001 module is designed to demonstrate the performance of the TR8001 ASH Transceiver at 4.8kbps, although other
data rates are possible with changes in on-board component values. See pin descriptions and refer to the TR8001 datasheet.
The DR8001 module may be mounted on a prototype assembly using standard 0.1” spacing, 10-pin headers spaced 0.9”
apart.
2G Mode Operation
The DR8001 may operate in 2G mode. See pin 15 description and Power-up Mode Select (J2) section for mode select
details. In 2G mode, the CFGCLK pin (18) and CFGDAT pin (17) operate as CTRL0 and CTRL1, respectively, just as for
second-generation devices. The CFGCLK and CFGDAT pins are a high impedance input allowing external control for 2G
configuration. The logic levels on CFGCLK (CTRL0) and CFGDAT (CTRL1) control the default 2G operation as shown
below:
CFGCLK (CNTRL0)
0
1
0
1
CFGDAT (CNTRL1)
0
0
1
1
MODE
SLEEP
TX OOK
TX ASK
RX
J5 Header
J2 Header
Current Consumption Monitor (J5)
The current consumption of the TR8001 device may be monitored by removing J5 and connecting an ammeter across the terminals. When
J5 is removed it isolates the TR8001 from VCC powering the on-board processor to give a true reading of the current consumption of only
the TR8001 without the additional current usage of the processor. J5 must be installed to power the TR8001 if not using the header for current
measurement.
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DR8001-071107
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