DR7001-EV Datasheet, PDF (4/8 Pages) Murata Manufacturing Co., Ltd. – 315.00 MHz Transceiver Evaluation Module

Pin
Name
In/Out
Description
11
SVEN
Logic Input (CMOS compatible). This pin, in 3G mode, enables the Start Vector Recognition circuit. The
In
TR7001 will not output a recovered clock on RXDCLK (pin 16) until the start vector, 0xE2E2, has been recog-
nized. Pull this pin ‘High’ to enable Start Vector Recognition. Pull this pin ‘Low’ then ‘High’ to reset the Start
Vector Recognition circuit. Do not allow this pin to float.
12
Not Used
Keep this pin pulled ‘Low’.
13
Not Used
Keep this pin pulled ‘Low’.
14
4.8KBPS/
19.2KBPS
Logic Input (CMOS compatible). This pin, in 3G mode, selects the receive data rate of the DR7001-EV. Pull
In
this pin ‘High’ to select 4.8kbps. Pull this pin ‘Low’ to select 19.2kbps. Do not allow this pin to float.
NOTE: Operating at 19.2kbps will require the value of C4, C5 and R4 to change to accommodate the higher
data rate. See the TR7001 datasheet for recommended component values.
15
3G SEL
Logic Input (CMOS compatible). This pin sets the processor to operate in 3G mode. The power-up operating
configuration of the TR7001 device is controlled by the J2 jumper setting. When DC power is applied to the
In
DR7001-EV with J2 installed across 2-3, this pin should be pulled ‘High’ immediately after power-up to initiate
3G mode. Failure to pull pin 15 ‘High’ after power-up will cause the processor to remain inactive. Pulling this
pin ‘High’ wakes the processor for 3G mode operation. When DC power is applied to the DR7001-EV with J2
installed across 1-2, this pin should be held ‘Low’ to operate in 2G mode. Do not allow this pin to float.
16
RXDCLK
RXDCLK is the clock output from the data and clock recovery circuit. RXDCLK is a CMOS output. When the
radio’s internal data and clock recovery circuit is not used, RXDCLK is a steady low value. When the internal
Out
data and clock recovery is used, RXDCLK is low until a packet start symbol is detected at the output of the
data slicer. Each bit following the start symbol is output at RXDATA on the rising edge of a RXDCLK pulse,
and is stable for reading on the falling edge of the RXDCLK pulse. Once RXDCLK is activated by the detec-
tion of a start symbol, it remains active until SVEN (pin 11) is reset. See Pin 11 description.
In 3G control mode, CFGDAT is a bi-directional CMOS logic pin. When CFG (Pin 19) is set to a logic 1, con-
figuration data can be clocked into or out of the radio’s configuration registers through CFGDAT using CFG-
CLK (Pin 18). Data clocked into CFGDAT is transferred to a control register each time a group of 8 bits is
received. Pulses on CFGCLK are used to clock configuration data into and out of the radio through CFGDAT.
17
CFGDAT
In/Out When writing through CFGDAT, a data bit is clocked into the radio on the rising edge of a CFGCLK pulse.
When reading through CFGDAT, data is output on the rising edge of the CFGCLK pulse and is stable for read-
ing on the falling edge of the CFGCLK. Refer to the TR7001 datasheet for detailed timing. This pin is a high
impedance input (CMOS compatible) in 2G mode. This pin must be held at a logic level. Do not allow this pin
to float.
In 3G control mode, pulses on CFGCLK are used to clock configuration data into and out of the radio through
CFGDAT (Pin 17). When writing to CFGDAT, a data bit is clocked into the radio on the rising edge of a CFG-
18
CFGCLK
In/Out CLK pulse. When reading through CFGDAT, data is stable for reading on the falling edge of the CFGCLK.
Refer to the TR7001 datasheet for detailed timing. This pin is a high impedance input (CMOS compatible) in
2G mode. Do not allow this pin to float.
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DR7001-EV - 4/8/08