DR8000-EV Datasheet, PDF (3/8 Pages) Murata Manufacturing Co., Ltd. – 916.50 MHz Transceiver Evaluation Module

916.50 MHz
Transceiver Module
Pin
1,4,20
19
Name
GND
VCC
2
PKDET
3
BBOUT
5
RXDATA
6
TXMOD
7
LPFADJ
In/Out
-
-
Out
Out
Out
In
In
GND is the ground pin.
VCC is a positive supply voltage pin.
Description
This pin is the peak detector output. A 0.022uF capacitor to ground (C5) sets the peak detector attack and
decay times, which have a fixed 1:1000 ratio. For most applications, these time constants should be coordi-
nated with the base-band time constant. For a given base-band capacitor C_BBO , the capacitor value C_PKD is:
C_PKD = 2.0* C_BBO , where C_BBO and C_PKD are in pF
A ±10% ceramic capacitor should be used at this pin. This time constant will vary between t_PKA and 1.5* t_PKA
with variations in supply voltage, temperature, etc. The capacitor is driven from a 200 ohm “attack” source,
and decays through a 200 K load. The peak detector is used to drive the “dB-below-peak” data slicer and the
AGC release function. The peak detector capacitor is discharged in the receiver power-down (sleep) mode
and in the transmit modes. See the description of Pin 3 below for further information. A 0.022uF capacitor is
installed for operation at 4.8kbps.
This pin is connected directly to the transceiver BBOUT pin. This pin drives the CMPIN pin through a coupling
capacitor, C_BBO = 0.01uF (C4), for internal data slicer operation at 4.8kbps.
C_BBO = 11.2*SP_MAX, where SP_MAX is the maximum signal pulse width in µs and C_BBO is in pF
The nominal output impedance of this pin is 1 K.The BBOUT signal changes about 10 mV/dB, with a peak-to-
peak signal level of up to 450 mV. The signal at BBOUT is riding on a 1.5 Vdc value that varies somewhat with
supply voltage and temperature, so it should be coupled through a capacitor to an external load. When an
external data recovery process is used with AGC, BBOUT must be coupled to the external data recovery pro-
cess and CMPIN by separate series coupling capacitors. The output impedance of this pin becomes very
high in sleep mode, preserving the charge on the coupling capacitor.
The value of C3 on the circuit board has been chosen to match typical data encoding schemes at 4.8 kbps. If
C4 is modified to support higher data rates and/or different data encoding schemes and PK DET is being
used, make the value of the peak detector capacitor C5 about 2x the value of C_BBO.
RXDATA is the receiver data output pin. It is a CMOS output. The signal on this pin can come from one of two
sources. The default source is directly from the output of the data slicer circuit. The alternate source is from
the radio’s internal data and clock recovery circuit. When the internal data and clock recovery circuit is used,
the signal on RXDATA is switched from the output of the data slicer to the output of the data and clock recov-
ery circuit when a packet start symbol is detected. Each recovered data bit is then output on the rising edge of
a RXDCLK pulse (Pin 16), and is stable for reading on the falling edge of the RXDCLK pulse.
The transmitter RF output voltage is proportional to the input current to this pin. A resistor in series with the
TXMOD input is normally used to adjust the peak transmitter output. Full transmitter power (10 mW) requires
about 315 µA of drive current. The transmitter output power P_O for a 3 Vdc supply voltage is approximately:
PO = 101*(I_TXM)², where PO is in mW and the modulation current I_TXM is in mA
The practical power control range is 10 to -50 dBm. A ±5% TXMOD resistor value is recommended. Internally,
this pin is connected to the base of a bipolar transistor with a small emitter resistor. The voltage at the TXMOD
input pin is about 0.87 volt with 315 uA of drive current. This pin accepts analog modulation and can be driven
with either logic level data pulses (unshaped) or shaped data pulses.
A series 6.2 kilohm resistor is installed to provide +10dBm average output power with a +3Vdc input.
This pin is the receiver low-pass filter bandwidth adjust. The filter bandwidth is set by a resistor R_LPF (R4)
between this pin and ground. The resistor value can range from 510 K to 3 K, providing a filter 3 dB bandwidth
f_LPF from 5 to 600 kHz. The resistor value is determined by:
R_LPF = (0.0006*f_LPF) ^-1.069 where R_LPF is in kilohms, and f_LPF is in kHz
A ±5% resistor should be used to set the filter bandwidth. This will provide a 3 dB filter bandwidth between
f_LPF and 1.3* f_LPF with variations in supply voltage, temperature, etc. The filter provides a three-pole, 0.05
degree equiripple phase response. A 470 kilohm resistor to GND is installed to provide a 3dB filter band-
width of 5.275kHz. Connect an external ±1%, 243kilohm resistor to GND for 19.2kbps operation.
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DR8000EV-071107
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