DR3300 Datasheet, PDF (3/5 Pages) RF Monolithics, Inc – 916.50 MHz Transceiver Module

Pin Descriptions
Pin
Name
Description
This pin is connected directly to the transceiver AGCCAP pin, which controls the AGC reset operation. To enable AGC opera-
tion (required for ASK transmission) an external capacitor is placed between this pin and ground. The capacitor sets the mini-
mum time the AGC will hold-in once it is engaged. The hold-in time is set to avoid AGC chattering. For a given hold-in time
t_AGH, the capacitor value C_AGC is:
C_AGC = 19.1* t_AGH, where t_AGH is in µs and C_AGC is in pF
1
AGC/VCC _{For 1 Mbps operation, a 100 pF ±10% ceramic capacitor should be used at this pin. The value of CAGC given above provides a}
hold-in time between t_AGH and 2.65* t_AGH, depending on operating voltage, temperature, etc. The hold-in time is chosen to
allow the AGC to ride through the longest run of zero bits that can occur in a received data stream. The AGC hold-in time can
be greater than the peak detector decay time, as discussed below. However, the AGC hold-in time should not be set too long,
or the receiver will be slow in returning to full sensitivity once the AGC is engaged by noise or interference. AGC operation also
depends on a functioning peak detector, as discussed below. The AGC capacitor is discharged in the transceiver power-down
(sleep) mode and in the transmit modes.
This pin is connected directly to the transceiver PKDET pin. This pin controls the peak detector operation. An external capacitor
between this pin and ground sets the peak detector attack and decay times, which have a fixed 1:1000 ratio. For 1 Mbps appli-
cations, the attack time constant should be set to 0.024 µs with a 100 pF capacitor to ground. (This adequately matches the
2
PK DET
peak detector decay time constant of 24 µs to the time constant of the 270 pF coupling capacitor C3.) A ±10% ceramic capaci-
tor should be used at this pin. The peak detector is used to drive the “dB-below-peak” data slicer and the AGC release function.
The AGC hold-in time can be extended beyond the peak detector decay time with the AGC capacitor, as discussed above. The
peak detector capacitor is discharged in the transceiver power-down (sleep) mode and in the transmit modes. See the descrip-
tion of Pin 3 below for further information.
This pin is connected directly to the transceiver BBOUT pin. On the circuit board, BBOUT also drives the transceiver CMPIN
pin through C3, a 270 pF coupling capacitor (t_BBC = 17.3 µs). RX BBO can also be used to drive an external data recovery pro-
cess (DSP, etc.). The nominal output impedance of this pin is 1 K. The RX BBO signal changes about 10 mV/dB, with a peak-
to-peak signal level of up to 675 mV. The signal at RX BBO is riding on a 1.1 Vdc value that varies somewhat with supply volt-
3
RX BBO
age and temperature, so it should be coupled through a capacitor to an external load. A load impedance of 50 K to 500 K in
parallel with no more than 10 pF is recommended. Note the AGC reset function is driven by the signal applied to CMPIN
through C3. When the transceiver is in power-down (sleep) or in a transmit mode, the output impedance of this pin becomes
very high, preserving the charge on the coupling capacitor(s). The value of C3 on the circuit board has been chosen to match
typical data encoding schemes at 1 Mbps. If C3 is modified to support different data rates and/or encoding schemes, make the
value of the peak detector capacitor about 1/3 the value of C3.
RX DATA is connected directly to the transceiver data output pin, RXDATA. This pin will drive a 10 pF, 500 K parallel load. The
peak current available from this pin increases with the receiver low-pass filter cutoff frequency. In the power-down (sleep) or
4
RX DATA transmit modes, this pin becomes high impedance. If required, a 1000 K pull-up or pull-down resistor can be used to establish
a definite logic state when this pin is high impedance (do not connect the pull-up resistor to a supply voltage higher than 3.5
Vdc or the transceiver will be damaged). This pin must be buffered to successfully drive low-impedance loads.
The TX IN pin is connected to the transceiver TXMOD pin through a 4.7 K resistor on the circuit board. Additional series resis-
tance will often be required between the modulation source and the TX IN pin, depending on the desired output power and
peak modulation voltage (3.3 K typical for a peak modulation voltage of 3 volts). Saturated output power requires about 450 µA
of drive current. Peak output power P_O for a 3 Vdc supply is approximately:
5
TX IN
P_O = 4.8*((V_TXH – 0.9)/(R_M + 4.7))², where P_O is in mW, peak modulation voltage V_TXH is in volts and external modulation
resistor R_M is in kilohms
This pin must be held low in the receive and sleep modes. Please refer to section 2.9 of the ASH Transceiver Designer’s Guide
for additional information.
6
GND This is a ground pin.
7
GND This is a ground pin.
This pin is the receiver low-pass filter bandwidth adjust, and is connected directly to the transceiver LPFADJ pin. R6 on the cir-
cuit board (1 K) is connected between LPFADJ and ground, and sets the receiver bandwidth for typical 1 Mbps operation. The
filter bandwidth can be increased by adding an external resistor in parallel with R6. The equivalent resistor value can range
from 1 K to 820 ohms, providing a filter 3 dB bandwidth f_LPF from 1.5 to 1.8 MHz. The 3 dB filter bandwidth is determined by:
8
LPF ADJ f_LPF = 1445/(1*R_LPF/(1 + R_LPF)), where R_LPF is in kilohms, and f_LPF is in kHz
A ±5% resistor should be used to set the filter bandwidth. This will provide a 3 dB filter bandwidth between f_LPF and 1.3* f_LPF
with variations in supply voltage, temperature, etc. The filter provides a three-pole, 0.05 degree equiripple phase response. The
peak drive current available from RXDATA increases in proportion to the filter bandwidth setting. Refer to sections 1.4.3, 2.5.1
and 2.6.1 in the ASH Transceiver Designer’s Guide for additional information on data rate adjustments.
www.RFM.com E-mail: [e-mail]
©2008 by RF Monolithics, Inc.
Page 3 of 5
DR3300 - 4/8/08