SI5317-EVB Datasheet, PDF (2/20 Pages) Murata Manufacturing Co., Ltd. – Si5317 EVALUATION BOARD

Si5317-EVB
1. Functional Block Diagram
A functional block diagram of the EVB is shown in Figure 1. The Si5317-EVB provides alarm and status outputs,
programmable output clock signal format (LVPECL, LVDS, CML, CMOS), selectable loop bandwidths, and ultra
low jitter.
The Si5317 accepts a single clock input ranging from 1 MHz to 710 MHz and generates two equal frequency clock
outputs ranging from 1 to 710 MHz. The clock frequency range and loop bandwidth are selectable from a simple
look-up table. The Si5317-EVB has a differential clock input that is AC terminated to 50  and then AC-coupled to
the Si5317. The two clock outputs are AC-coupled. The XA-XB reference is usually a 114.285 MHz crystal; but
there are provisions for an external XA-XB reference (either differential or single-ended). The device status are
available on a ribbon header and LEDs. Control pins are strapped using jumper headers for device configuration
and various board options. The board can be powered using either external power supplies or from a PC's USB
port. Refer to the Si5317 data sheet for technical details of the device.
Term*
Term*
Control
2x15
JUMPER
HEADER
XA
CKIN+
CKIN-
XB _CKOUT1+
CKOUT1-
CKOUT2+
CKOUT2-
Term*
Term*
Si5317
FRQTBL
FRQSEL[3:0]
BWSEL[1:0]
RATE[1:0]
SFOUT[1:0]
DBL2_BY
VDD
GND
INC
DEC
LOS
LOL
RST_B
3.3V
Header
Status/
Control
2x5
JUMPER
HEADER
Figure 1. Si5317 EVB Block Diagram
DUT Power
USB
+ Regulator
L
E
D
2
Rev. 0.1