DR5101 Datasheet, PDF (2/4 Pages) RF Monolithics, Inc – 315.00 MHz Receiver Module

Pin Desciptions
Pin
Name
Description
This pin is connected directly to the receiver AGCCAP pin. To disable AGC operation, this pin is tied to VCC. To enable AGC
operation, a capacitor is placed between this pin and ground. This pin controls the AGC reset operation. A capacitor between
this pin and ground sets the minimum time the AGC will hold-in once it is engaged. The hold-in time is set to avoid AGC chat-
tering. For a given hold-in time t_AGH, the capacitor value C_AGC is:
C_AGC = 19.1* t_AGH, where t_AGH is in µs and C_AGC is in pF
A ±10% ceramic capacitor should be used at this pin. The value of C_AGC given above provides a hold-in time between t_AGH and
1
AGC/VCC ^{2.65* tAGH, depending on operating voltage, temperature, etc. The hold-in time is chosen to allow the AGC to ride through the}
longest run of zero bits that can occur in a received data stream. The AGC hold-in time can be greater than the peak detector
decay time, as discussed below. However, the AGC hold-in time should not be set too long, or the receiver will be slow in
returning to full sensitivity once the AGC is engaged by noise or interference. The use of AGC is optional when using OOK
modulation with data pulses of at least 30 µs. Active or latched AGC operation is required for ASK modulation and/or for data
pulses of less than 30 µs. The AGC can be latched ON once engaged by connecting a 150 K resistor between this pin and
ground, instead of a capacitor. AGC operation depends on a functioning peak detector, as discussed below. The AGC capacitor
is discharged in the receiver power-down (sleep) mode. Note that provisions are made on the circuit board to install a jumper
between this pin and the junction of C2 and L3. Installing the jumper allows either this pin or Pin 9 to be used for the Vcc supply
when AGC operation is not required.
This pin is connected directly to the receiver PKDET pin. This pin controls the peak detector operation. A capacitor between
this pin and ground sets the peak detector attack and decay times, which have a fixed 1:1000 ratio. For most applications, the
attack time constant should be set to 6.4 ms with a 0.027 µF capacitor to ground. (This matches the peak detector decay time
constant to the time constant of the 0.1 µF coupling capacitor C3.) A ±10% ceramic capacitor should be used at this pin. The
2
PK DET peak detector is used to drive the "dB-below-peak" data slicer and the AGC release function. The AGC hold-in time can be
extended beyond the peak detector decay time with the AGC capacitor, as discussed above. Where low data rates and OOK
modulation are used, the "dB-below-peak" data slicer and the AGC are optional. In this case, the PKDET pin can be left uncon-
nected, and the AGC pin can be connected to VCC to reduce the number of external components needed. The peak detector
capacitor is discharged in the receiver power-down (sleep) mode. See the description of Pin 3 below for further information.
This pin is connected directly to the receiver BBOUT pin. On the circuit board, BBOUT also drives the receiver CMPIN pin
through C3, a 0.1 µF coupling capacitor (t_BBC = 6.4 ms). RX BBO can also be used to drive an external data recovery process
(DSP, etc.). The nominal output impedance of this pin is 1 K. The RX BBO signal changes about 10 mV/dB, with a peak-to-
peak signal level of up to 675 mV. The signal at RX BBO is riding on a 1.1 Vdc value that varies somewhat with supply voltage
3
RX BBO
and temperature, so it should be coupled through a capacitor to an external load. A load impedance of 50 K to 500 K in parallel
with no more than 10 pF is recommended. Note the AGC reset function is driven by the signal applied to CMPIN through C3.
When the receiver is in power-down (sleep) the output impedance of this pin becomes very high, preserving the charge on the
coupling capacitor(s). The value of C3 on the circuit board has been chosen to match typical data encoding schemes at 2.4
kbps. If C3 is modified to support higher data rates and/or different data encoding schemes and PK DET is being used, make
the value of the peak detector capacitor about 1/3 the value of C3.
RX DATA is connected directly to the receiver data output pin, RXDATA. This pin will drive a 10 pF, 500 K parallel load. The
peak current available from this pin increases with the receiver low-pass filter cutoff frequency. In the power-down (sleep) or
4
RX DATA receive mode, this pin becomes high impedance. If required, a 1000 K pull-up or pull-down resistor can be used to establish a
definite logic state when this pin is high impedance (do not connect the pull-up resistor to a supply voltage higher than 3.5 Vdc
or the receiver will be damaged). This pin must be buffered to successfully drive low-impedance loads.
5
NC
6, 7
GND
This pin is the receiver low-pass filter bandwidth adjust, and is connected directly to the receiver LPFADJ pin. R6 on the circuit
board (330 K) is connected between LPFADJ and ground will be in parallel with any external resistor connected to LPF ADJ.
The filter bandwidth is set by the parallel resistance of R6 and the external resistor (if used). The equivalent resistor value can
range from 330 K to 820 ohms, providing a filter 3 dB bandwidth f_LPF from 4.4 kHz to 1.8 MHz. The 3 dB filter bandwidth is
determined by:
f_LPF = 1445/ (330*R_LPF/(330 + R_LPF)), where R_LPF is in kilohms, and f_LPF is in kHz
8
LPF ADJ
A ±5% resistor should be used to set the filter bandwidth. This will provide a 3 dB filter bandwidth between f_LPF and 1.3* f_LPF
with variations in supply voltage, temperature, etc. The filter provides a three-pole, 0.05 degree equiripple phase response. The
peak drive current available from RXDATA increases in proportion to the filter bandwidth setting. As shipped, the receiver mod-
ule is set up for nominal 2.4 kbps operation. An external resistor can be added between Pin 8 and ground to support higher
data rates. Preamble training times will not be decreased, however, unless C3 is replaced with a smaller capacitor value (see
the descriptions of Pins 2 and 3 above). Refer to sections 1.4.3, 2.5.1 and 2.6.1 in the ASH Transceiver Designer's Guide for
additional information on data rate adjustments.
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DR5101 - 4/8/08