SCA1000 Datasheet, PDF (10/14 Pages) VTI technologies – Accelerometer

SCA1000 Series
Read Y-channel acceleration (RDAY) accesses the AD converted Y-channel (Channel 2)
acceleration signal stored in acceleration data register Y.
During normal operation, acceleration data registers are reloaded every 150 µs. The load operation
is disabled whenever the CSB signal is low, hence CSB must stay high at least 150 µs prior the
RDAX command in order to guarantee correct data. Data output is an 11-bit digital word that is fed
out MSB first and LSB last.
Figure 6. Command and 11 bit acceleration data transmission over the SPI
2.4 Self Test and Failure Detection Modes
To ensure reliable measurement results the SCA1000 has continuous interconnection failure and
calibration memory validity detection. A detected failure forces the output signal close to power
supply ground or VDD level, outside the normal output range. The normal output ranges are:
analog 0.25-4.75 V (@Vdd=5V) and SPI 102...1945 counts.
The calibration memory validity is verified by continuously running parity check for the control
register memory content. In the case where a parity error is detected, the control register is
automatically re-loaded from the EEPROM. If a new parity error is detected after re-loading data
both analog output voltages are forced to go close to ground level (<0.25 V) and SPI outputs go
below 102 counts.
The SCA1000 also includes a separate self test mode. The true self test simulates acceleration, or
deceleration, using an electrostatic force. The electrostatic force simulates acceleration that is high
enough to deflect the proof mass to the extreme positive position, and this causes the output signal
to go to the maximum value. The self test function is activated either by a separate on-off
command on the self test input, or through the SPI.
The self-test generates an electrostatic force, deflecting the sensing element’s proof mass, thus
checking the complete signal path. The true self test performs following checks:
 Sensing element movement check
 ASIC signal path check
 PCB signal path check
 Micro controller A/D and signal path check
The created deflection can be seen in both the SPI and analogue output. The self test function is
activated digitally by a STX or STY command, and de-activated by a MEAS command. Self test
can be also activated applying logic”1” (positive supply voltage level) to ST pins (pins 9 & 10) of
Murata Electronics Oy
www.muratamems.fi
Subject to changes
Doc. nr. 82 1566 00
10/14
Rev.A