SC3049B Datasheet, PDF (1/2 Pages) Murata Manufacturing Co., Ltd. – 700.0 MHz Differential Sine-Wave Clock

• Quartz SAW Frequency Stability
• Fundamental Fixed Frequency
• Very Low Jitter and Power Consumption
• Rugged, Miniature, Surface-Mount Case
• Low-Voltage Power Supply (3.3 VDC)
This digital clock is designed for use with high-speed timing systems. Fundamental-mode oscillation is made
possible by surface-acoustic-wave (SAW) technology. The design results in low jitter, compact size, and low
power consumption. Differential outputs provide a sine wave that is capable of driving 50 Ω loads.
Absolute Maximum Ratings
Rating
Value
Units
Power Supply Voltage (V_CC at Terminal 1)
Input Voltage (ENABLE at Terminal 8)
0 to +4.0
0 to +4.0
VDC
VDC
Case Temperature (Powered or Storage)
-40 to +85
°C
SC3049B
700.0 MHz
Differential
Sine-Wave
Clock
Electrical Characteristics
Characteristic
Output Frequency
Q and Q Output
Q and Q Period Jitter
Output (Disabled)
Absolute Frequency
Tolerance from 700.000 MHz
Voltage into 50Ω (VSWR ≤ 1.2)
Operating Load VSWR
Symmetry
Harmonic Spurious
Nonharmonic Spurious
Start Up Time
No Noise on V_CC
200 mV_P-P from 1 MHz to 1/2 f_O on
Amplitude into 50 Ω
Output DC Resistance (between Q & Q)
ENABLE (Terminal 14)
Input HIGH Voltage
Input LOW Voltage
Input HIGH Current
Input LOW Current
Propagation Delay
DC Power Supply
Operating Voltage
Operating Current
Operating Ambient Temperature
Lid Symbolization (YY = Year, WW = Week)
SMC-8 Case
Sym
f_O
∆f_O
V_O
V_IH
V_IL
I_IH
I_IL
t_PD
V_CC
I_CC
T_A
Notes
1, 2
1, 3
3, 4, 5
3, 4, 6
1, 10
3, 4, 6, 7
3, 4, 7, 8
3, 9
3
3, 9
1, 3
1, 3
Minimum
699.825
Typical
Maximum
700.175
±250
0.60
.85
2:1
49
51
-30
-60
38
15
30
35
75
50
V_CC-0.1
V_CC
V_CC+0.1
0.0
0.20
3
5
-1
1
+3.13
+3.30
+3.47
20
40
0
+70
RFM SC3049B YYWW
Units
MHz
ppm
V_P-P
%
dBc
dBc
µs
ps_P-P
ps_P-P
mV_P-P
KΩ
V
V
mA
mA
ms
VDC
mA
°C
CAUTION: Electrostatic Sensitive Device. Observe precautions for handling.
NOTES:
1. Unless otherwise noted, all specifications include any combination of load
noise on V_CC or mechanical vibration are not included. Dedicated external
VSWR, VCC, and TA. In addition, Q and Q are terminated into 50 Ω loads
voltage regulation and careful PCB layout are recommended for optimum
to ground. (See: Typical Test Circuit.)
performance.
2. One or more of the following United States patents apply: 4,616,197;
7. Applies to period jitter of Q and Q. Measurements are made with the
4,670,681; 4,760,352.
Tektronix CSA803 signal analyzer with at least 1000 samples.
3.
4.
5.
6.
The design, manufacturing process, and specifications of this device are
subject to change without notice.
Only under the nominal conditions of 50 Ω load impedance with VSWR ≤
1.2 and nominal power supply voltage.
Symmetry is defined as the pulse width (in percent of total period)
measured at the 50% points of Q or Q. (See: Timing Definitions.)
Jitter and other spurious outputs induced by externally generated electrical
8.
9.
Period jitter measured with a 200 mV_P-P sine wave swept from 1 MHz to
one-half of f_O at the V_CC power supply terminal.
The outputs are enabled when Terminal 8 is at logic HIGH. Propagation
delay is defined as the time from the 50% point on the rising edge of
ENABLE to the 90% point on the rising edge of the output amplitude or as
the fall time from the 50% point to the 10% point. (SEE: Timing
Definitions.)
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SC3049B - 1/26/11