SC3046B-5 Datasheet, PDF (1/2 Pages) Murata Manufacturing Co., Ltd. – 933.12 MHz Differential Sine-Wave Clock

®
• Quartz SAW Frequency Stability
• Fundamental Fixed Frequency
• Very Low Jitter and Power Consumption
• Rugged, Miniature, Surface-Mount Case
• Low-Voltage Power Supply (3.3 VDC)
This digital clock is designed for use in high-speed communications timing systems. Fundamental-mode os-
cillation is made possible by surface-acoustic-wave (SAW) technology. The design results in low jitter, com-
pact size, and low power consumption. Differential outputs provide a sine wave that is capable of driving 50 Ω
loads.
SC3046B-5
933.12 MHz
Differential
Sine-Wave
Clock
Rating
Power Supply Voltage (V_CC at Terminal 1)
Input Voltage (ENABLE at Terminal 8)
Case Temperature (Powered or Storage)
Electrical Characteristics
Output Frequency
Q and Q Output
Q and Q Period Jitter
Output (Disabled)
Characteristic
Absolute Frequency
Variation over Temperture
Power into 50Ω (VSWR ≤ 1.2)
Operating Load VSWR
Symmetry
Harmonic Spurious
Nonharmonic Spurious
Start Up Time
No Noise on V_CC
200 mV_P-P from 1 MHz to ½ f_O on
Amplitude into 50 Ω
Output DC Resistance (between Q & Q)
ENABLE (Terminal 14)
Input HIGH Voltage
Input LOW Voltage
Input HIGH Current
Input LOW Current
Propagation Delay
DC Power Supply
Operating Voltage
Operating Current
Operating Ambient Temperature
Lid Symbolization (YY = Year, WW = Week)
Value
0 to +4.0
0 to +4.0
-40 to +85
Units
VDC
VDC
°C
SMC-8B Case
Sym
f_O
V_O
V_IH
V_IL
I_IH
I_IL
t_PD
V_CC
I_CC
T_A
Notes
1, 2
Minimum
932.725
Typical
Maximum
933.300
70
0.5
3.0
6.0
1, 3
2:1
3, 4, 5
49
51
-30
3, 4, 6
-60
1, 10
30
3, 4, 6, 7
15
30
3, 4, 7, 8
35
3, 9
75
3
50
V_CC-0.1
0.0
V_CC
V_CC+0.1
0.20
3, 9
3
5
-1
1
+3.13
+3.30
+3.47
1, 3
25
45
1, 3
10
+60
RFM SC3046B-5 933.12 MHz YYWW
Units
MHz
ppm
dBm
V_P-P
%
dBc
dBc
µs
ps_P-P
ps_P-P
mV_P-P
KΩ
V
V
mA
mA
ms
VDC
mA
°C
CAUTION: Electrostatic Sensitive Device. Observe precautions for handling.
NOTES:
1. Unless otherwise noted, all specifications are at 25 ± 3°C and include any combi-
regulation and careful PCB layout are recommended for optimum performance.
nation of load VSWR and VCC. In addition, Q and Q are terminated into 50 Ω 7. Applies to period jitter of Q and Q. Measurements are made with the Tektronix
loads to ground. (See: Typical Test Circuit.)
CSA803 signal analyzer with at least 1000 samples.
2. One or more of the following United States patents apply: 4,616,197; 4,670,681; 8. Period jitter measured with a 200 mV_P-P sine wave swept from 1 MHz to one-half
4,760,352.
of f_O at the V_CC power supply terminal.
3. The design, manufacturing process, and specifications of this device are subject _{9. The outputs are enabled when Terminal 8 is at logic HIGH. Propagation delay is}
to change without notice.
defined as the time from the 50% point on the rising edge of ENABLE to the 90%
4. Only under the nominal conditions of 50 Ω load impedance with VSWR ≤ 1.2 and
point on the rising edge of the output amplitude or as the fall time from the 50%
nominal power supply voltage.
point to the 10% point. (SEE: Timing Definitions.)
5. Symmetry is defined as the pulse width (in percent of total period) measured at _{10. The start up time is definded as the time from when power is applied to terminals}
the 50% points of Q or Q. (See: Timing Definitions.)
1 and 8 (90% of 3.3V) until power out from Q and Qbar reaches 90% of Qout
6. Jitter and other spurious outputs induced by externally generated electrical noise
level.
on V_CC or mechanical vibration are not included. Dedicated external voltage
RF Monolithics, Inc. Phone: [phone]
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SC3046B-5-051904
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