SC3041B Datasheet, PDF (1/2 Pages) RF Monolithics, Inc – 300.0 MHz Differential Sine-Wave Clock

SC3041B
• Quartz SAW Frequency Stability
• Fundamental Fixed Frequency
• Excellent Jitter and Symmetry
• Rugged, Miniature, Surface-Mount Case
• Low-Voltage Power Supply (3.3 VDC)
• Directive 2002/95/EC (ROHS) Compliant by June, 2006
This digital clock is designed for use in abrizio’s chipset for Terabit Router applications. Fundamental-mode
oscillation is made possible by surface-acoustic-wave (SAW) technology. The design results in low jitter,
compact size, and low power consumption. Differential outputs provide a sine wave that is made to drive 50 Ω
loads.
Absolute Maximum Ratings
Rating
Power Supply Voltage (V_CC at Terminal 1)
Input Voltage (ENABLE at Terminal 8)
Value
0 to +4.0
0 to +4.0
Units
VDC
VDC
Case Temperature (Powered or Storage)
-40 to +85
°C
300.0 MHz
Differential
Sine-Wave
Clock
SMC-8 Case
Electrical Characteristics
Characteristic
Output Frequency
Q and Q Output
Q and Q Period Jitter
Output (Disabled)
Absolute Frequency
Tolerance from 286.0 MHz
Voltage into 50Ω (VSWR ≤ 1.2)
Operating Load VSWR
Symmetry
Harmonic Spurious
Nonharmonic Spurious
No Noise on V_CC
200 mV_P-P from 1 MHz to ½ f_O on
Amplitude into 50 Ω
Output DC Resistance (between Q & Q)
ENABLE (Terminal 14)
Input HIGH Voltage
Input LOW Voltage
Input HIGH Current
Input LOW Current
Propagation Delay
DC Power Supply
Operating Voltage
Operating Current
Operating Ambient Temperature
Lid Symbolization (YY = Year, WW = Week)
Sym
f_O
Δf_O
V_O
V_IH
V_IL
I_IH
I_IL
t_PD
V_CC
I_CC
T_A
Notes
1, 2
Minimum
299.940
Typical
Maximum
300.060
±200
0.5
4.5
1, 3
2:1
3, 4, 5
49
51
3, 4, 6
-25
-20
-60
3, 4, 6, 7
15
30
3, 4, 7, 8
35
3, 9
75
3
100
V_CC-0.1
0.0
V_CC
V_CC+0.1
0.20
3, 9
3
5
-1
1
+3.13
+3.30
+3.47
1, 3
18
40
1, 3
0
+70
RFM SC3041B 300.00 MHz YYWW
Units
MHz
ppm
dBm
%
dBc
dBc
ps_P-P
ps_P-P
mV_P-P
KΩ
V
V
mA
mA
ms
VDC
mA
°C
CAUTION: Electrostatic Sensitive Device. Observe precautions for handling.
NOTES:
1. Unless otherwise noted, all specifications include any combination of
load VSWR, VCC, and TA. In addition, Q and Q are terminated into
50 Ω loads to ground. (See: Typical Test Circuit.)
2. One or more of the following United States patents apply: 4,616,197;
4,670,681; 4,760,352.
3. The design, manufacturing process, and specifications of this device
are subject to change without notice.
4. Only under the nominal conditions of 50 Ω load impedance with
VSWR ≤ 1.2 and nominal power supply voltage.
5. Symmetry is defined as the pulse width (in percent of total period)
measured at the 50% points of Q or Q. (See: Timing Definitions.)
6. Jitter and other spurious outputs induced by externally generated
electrical noise on V_CC or mechanical vibration are not included.
Dedicated external voltage regulation and careful PCB layout are
recommended for optimum performance.
7. Applies to period jitter of Q and Q. Measurements are made with the
Tektronix CSA803 signal analyzer with at least 1000 samples.
8. Period jitter measured with a 200 mV_P-P sine wave swept from 1 MHz
to one-half of f_O at the V_CC power supply terminal.
9. The outputs are enabled when Terminal 8 is at logic HIGH.
Propagation delay is defined as the time from the 50% point on the
rising edge of ENABLE to the 90% point on the rising edge of the
output amplitude or as the fall time from the 50% point to the 10%
point. (SEE: Timing Definitions.)
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©2008 by RF Monolithics, Inc.
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SC3041B - 3/27/08