OKDH-T Datasheet, PDF (30/38 Pages) Murata Power Solutions Inc. – 40A Digital PoL DC-DC Converter Series

OKDx-T/40-W12-xxx-C
40A Digital PoL DC-DC Converter Series
figure below. Recommended resistor values for hard-wiring PMBus
addresses are shown in the table. 1% tolerance resistors are required.
SA0
SA1
PREF
R _SA1 R _SA0
Schematic of connection of address resistor.
Index
0
1
2
3
4
5
6
7
8
9
10
11
12
R_SA [kΩ]
10
11
12.1
13.3
14.7
16.2
17.8
19.6
21.5
23.7
26.1
28.7
31.6
Index
13
14
15
16
17
18
19
20
21
22
23
24
The PMBus address follows the equation below:
R_SA [kΩ]
34.8
38.3
42.2
46.4
51.1
56.2
61.9
68.1
75
82.5
90.9
100
Eq. 7. PMBus Address (decimal) = 25 x (SA1 index) + (SA0 index)
The user can theoretically configure up to 625 unique PMBus
addresses, however the PMBus address range is inherently limited to
128. Therefore, the user should use index values 0 - 4 on the SA1 pin
and the full range of index values on the SA0 pin, which will provide
125 device address combinations. The user shall also be aware
of further limitations of the address space as stated in the SMBus
Specification.
Note that address 0x4B is allocated for production needs and
cannot be used.
Optional PMBus Addressing
Alternatively the PMBus address can be defined by connecting the
SA0/SA1 pins according to the table below. SA1 = open for products
with no SA1 pin.
SA0
low
open
high
low
20h
21h
22h
SA1
open
23h
24h
25h
high
26h
27h
Reserved
Low = Shorted to PREF
Open = High impedance
High = Logic high, GND as reference,
Logic High definitions see Electrical Specification
Reserved Addresses
Address 4Bh is allocated for production needs and cannot be used.
Addresses listed in the table below are reserved or assigned
according to the SMBus specification and may not be usable. Refer to
the SMBus specification for further information.
Address
(decimal)
0
1
2
3-7
8
9-11
12
40
44-45
55
64-68
72-75
97
120-123
124-127
Comment
General Call Address / START byte
CBUS address
Address reserved for different bus format
Reserved for future use
SMBus Host
Assigned for Smart Battery
SMBus Alert Response Address
Reserved for ACCESS.bus host
Reserved by previous versions of the SMBus specification
Reserved for ACCESS.bus default address
Reserved by previous versions of the SMBus specification
Unrestricted addresses
SMBus Device Default Address
10-bit slave addressing
Reserved for future use
I²C/SMBus – Timing
Setup and hold times timing diagram
The setup time, tset, is the time data, SDA, must be stable before the
rising edge of the clock signal, SCL. The hold time thold, is the time
data, SDA, must be stable after the rising edge of the clock signal,
SCL. If these times are violated incorrect data may be captured or
meta-stability may occur and the bus communication may fail. When
configuring the product, all standard SMBus protocols must be fol-
lowed, including clock stretching. Refer to the SMBus specification, for
SMBus electrical and timing requirements.
This product does not support the BUSY flag in the status commands
to indicate product being too busy for SMBus response. Instead a bus-
free time delay according to this specification must occur between
every SMBus transmission (between every stop & start condition). In
case of storing the RAM content into the internal non-volatile memory
(commands STORE_USER_ALL and STORE_DEFAULT_ALL) an addi-
tional delay of 100 ms has to be inserted. A 100 ms delay should be
inserted after a restore from internal non-volatile memory (commands
RESTORE_DEFAULT_ALL and RESTORE_USER_ALL).
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