OKDX-T Datasheet, PDF (20/38 Pages) Murata Power Solutions Inc. – 40A Digital PoL DC-DC Converter Series

OKDx-T/40-W12-xxx-C
40A Digital PoL DC-DC Converter Series
Input Under Voltage Lockout, UVLO
The product monitors the input voltage and will turn-on and turn-off at
configured levels. The default turn-on input voltage level setting is 4.20 V,
whereas the corresponding turn-off input voltage level is 3.85 V. Hence,
the default hys
teresis between turn-on and turn-off input voltage is 0.35 V.
Once an input turn-off condition occurs, the device can respond in a
number of ways as follows:
1. Continue operating without interruption. The unit will continue to
operate as long as the input voltage can be supported. If the input
voltage continues to fall, there will come a point where the unit will
cease to operate.
2. Continue operating for a given delay period, followed by shutdown if
the fault still exists. The device will remain in shutdown until
instructed to restart.
3. Initiate an immediate shutdown until the fault has been cleared. The
user can select a specific number of retry attempts.
The default response from a turn-off is an immediate shutdown of the
device. The device will continuously check for the presence of the fault
condition. If the fault condition is no longer present, the product will be re-
enabled. The turn-on and turn-off levels and response can be reconfigured
using the PMBus interface.
Remote Control
Vext
CTRL
GND
The product is equipped with a remote
control function, i.e., the CTRL pin. The
remote control can be connected to
either the primary negative input
connection (GND) or an external
voltage (Vext), which is a 3 - 5 V
positive supply voltage in accordance
to the SMBus Specification version
2.0.
The CTRL function allows the product to be turned on/off by an external
device like a semiconductor or mechanical switch. By default the product
will turn on when the CTRL pin is left open and turn off when the CTRL pin
is applied to GND. The CTRL pin has an internal pull-up resistor. When the
CTRL pin is left open, the voltage generated on the CTRL pin is max 5.5 V.
If the device is to be synchronized to an external clock source, the clock
frequency must be stable prior to asserting the CTRL pin.
The product can also be configured using the PMBus interface to be
“Always on ” or turn on/off can be performed with PMBus commands.
Input and Output Impedance
The impedance of both the input source and the load will interact with the
impedance of the product. It is important that the input source has low
characteristic impedance. The performance in some applications can be
enhanced by addition of external capacitance as described under External
Decoupling Capacitors. If the input voltage source contains significant
inductance, the addition a capacitor with low ESR at the input of the
product will ensure stable operation.
External Capacitors
Input capacitors:
The input ripple RMS current in a buck converter is equal to
I _inputRMS = I _load D (1–D),
where I_load is the output load current and D is the duty cycle. The
maximum load ripple current becomes I_load 2 . The ripple current is
divided into three parts, i.e., currents in the input source, external input
capacitor, and internal input capacitor. How the current is divided depends
on the impedance of the input source, ESR and capacitance values in the
capacitors. A minimum capacitance of 300 μF with low ESR is
recommended. The ripple current rating of the capacitors must follow
Eq. 1. For high-performance/transient applications or wherever the input
source performance is degraded, additional low ESR ceramic type
capacitors at the input is recommended. The additional input low ESR
capacitance above the minimum level insures an optimized performance.
Output capacitors:
When powering loads with significant dynamic current requirements, the
voltage regulation at the point of load can be improved by addition of
decoupling capacitors at the load.
The most effective technique is to locate low ESR ceramic and electrolytic
capacitors as close to the load as possible, using several capacitors in
parallel to lower the effective ESR. The ceramic capacitors will handle high-
frequency dynamic load changes while the electrolytic capacitors are used
to handle low frequency dynamic load changes. Ceramic capacitors will
also reduce high frequency noise at the load.
It is equally important to use low resistance and low inductance PWB
layouts and cabling.
External decoupling capacitors are a part of the control loop of the product
and may affect the stability margins.
Stable operation is guaranteed for the following total capacitance C_O in
the output decoupling capacitor bank where
Eq. 2. C_O > @ C_min ,C_max >470, 30000@ μF.
The decoupling capacitor bank should consist of capacitors which has a
capacitance value larger than C t C_min and has an ESR range of
Eq. 3. ESR > @ ESR_min , ESR_max >5, 30@ mΩ
The control loop stability margins are limited by the minimum time constant
W _min of the capacitors. Hence, the time constant of the capacitors should
follow Eq. 4.
Eq. 4. W t W _min C_min ESR_min 2.35 P s
This relation can be used if your preferred capacitors have parameters
outside the above stated ranges in Eq. 2 and Eq.3.
x If the capacitors capacitance value is C  C_min one must use at least
N capacitors where
N
t
ª C_min
«« _C
º
»»
and
ESR
t
ESR_min
C_min
C
.
x If the ESR value is ESR ! ESR_max one must use at least N capacitors
of that type where
www.murata-ps.com/support
MDC_OKDx-T/40-W12-xxx-C.A05 Page 20 of 38